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glucose meter 8-bit flash mcu HT45F65/ht45f66/ht45f67 revision: v1.60 date: ? ove ?? e ? ??? ? 01 ? ? ove ?? e ? ??? ? 01 ?
rev. 1.60 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu table of contents eates cpu featu ? es ........................................................................................................................ 7 pe ? iphe ? al featu ? es ................................................................................................................. 7 gene?al desc?iption ......................................................................................... 8 s election ta?le ................................................................................................. 8 block diag?a? .................................................................................................. 9 pin assign?ent ........... ................................................................................... 10 pin desc?iption .......... .................................................................................... 1? a?solute maxi?u? ratings .......................................................................... 18 d.c. cha?acte?istics ....................................................................................... 18 a.c. cha?acte?istics ....................................................................................... ?0 adc & bandgap elect?ical cha?acte?istics ................................................. ?1 powe?-on reset cha?acte?istics ........... ........................................................ ?1 lcd d.c. cha?acte?istics .......... .................................................................... ?? audio dac elect?ical cha?acte?istics .......................................................... ?? 10-?it dac elect?ical cha?acte?istics .......................................................... ?? op amplifer electrical characteristics clocking and pipelining ......................................................................................................... ?? p ? og ? a ? c ounte ? ................................................................................................................... ?? stack ..................................................................................................................................... ? 6 a ? ith ? etic and logic unit C alu .......................................................................................... ? 6 flash p?og?a? me?o?y ................................................................................ ?7 st ? uctu ? e ............................................................................................................................... ? 7 special vecto ? s ..................................................................................................................... ? 7 look-up ta ? le ............. .......................................................................................................... ? 8 ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ? 8 in ci ? cuit p ? og ? a ?? ing C icp ............................................................................................... ? 9 in application p ? og ? a ?? ing C iap ........................................................................................ 30 on chip de ? ug suppo ? t (ocds) ............. ............................................................................. 37 ram data me?o?y ......................................................................................... 38 st ? uctu ? e ............................................................................................................................... 38
rev. 1.60 ? ?ove??e? ??? ?01? rev. 1.60 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu special function register description ........................................................ 40 indi ? ect add ? essing registe ? s C iar0 ? iar1 ........................................................................ ? 0 me ? o ? y pointe ? s C mp0 ? mp1 ............................................................................................. ? 0 bank pointe ? C bp ................................................................................................................ ? 1 accu ? ulato ? C acc .............................................................................................................. ?? p ? og ? a ? counte ? low registe ? C pcl ................................................................................. ?? look-up ta ? le registe ? s C tblp ? tbhp ? tblh .................................................................... ?? status registe ? C status .................................................................................................... ? 3 oscillator ........................................................................................................ 44 oscillato ? ove ? view ............. ................................................................................................. ?? system clock confgurations ................................................................................................ ?? exte ? nal c ? ystal/ce ? a ? ic oscillato ? C hxt ........................................................................... ?? exte ? nal rc oscillato ? C erc (ht ?? f66/ht ?? f67) ............................................................. ? 6 inte ? nal rc oscillato ? C hirc ............. .................................................................................. ? 6 exte ? nal 3 ? .768khz c ? ystal oscillato ? C lxt ............. ........................................................... ? 6 lxt oscillato ? low powe ? function ..................................................................................... ? 7 inte ? nal 3 ? khz oscillato ? C lirc .......................................................................................... ? 8 supple ? enta ? y oscillato ? s ................................................................................................... ? 8 operating modes and system clocks ......................................................... 48 syste ? clocks ...................................................................................................................... ? 8 syste ? ope ? ation modes ..................................................................................................... ? 0 cont ? ol registe ? .................................................................................................................... ? 1 fast wake -up ........................................................................................................................ ?? ope ? ating mode switching ................................................................................................... ?? stand ? y cu ?? ent conside ? ations .......................................................................................... ? 7 wake-up ................................................................................................................................ ? 7 p ? og ? a ?? ing conside ? ations ............. .................................................................................. ? 8 syste ? clock output ............................................................................................................ ? 8 watchdog timer ........... .................................................................................. 59 watchdog ti ? e ? clock sou ? ce .............................................................................................. ? 9 watchdog ti ? e ? cont ? ol registe ? ............. ............................................................................ ? 9 watchdog ti ? e ? ope ? ation ................................................................................................... 60 reset and initialisation ................................................................................. 61 reset functions ............. ...................................................................................................... 61 reset initial conditions ......................................................................................................... 6 ? input/output ports ........................................................................................ 74 pull-high resisto ? s ................................................................................................................ 7 ? po ? t a wake-up ............. ........................................................................................................ 77 i/o po ? t cont ? ol registe ? s ..................................................................................................... 77 pin- ? e ? apping functions ..................................................................................................... 79 pin- ? e ? apping registe ? s ....................................................................................................... 79 i/o pin st ? uctu ? es .................................................................................................................. 90 p ? og ? a ?? ing conside ? ations ............. .................................................................................. 90
rev. 1.60 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu timer modules C tm .......... ........................................................................... 91 int ? oduction .......................................................................................................................... 91 tm ope ? ation ............. .......................................................................................................... 91 tm clock sou ? ce ............. ..................................................................................................... 9 ? tm inte ?? upts ........................................................................................................................ 9 ? tm exte ? nal pins .................................................................................................................. 9 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 93 compact type tm C ctm .............................................................................. 94 co ? pact tm ope ? ation ........................................................................................................ 9 ? co ? pact type tm registe ? desc ? iption ................................................................................ 9 ? co ? pact type tm ope ? ating modes ................................................................................... 99 standard type tm C stm .......... ................................................................. 105 standa ? d tm ope ? ation ............. ......................................................................................... 10 ? standa ? d type tm registe ? desc ? iption ............................................................................ 106 standa ? d type tm ope ? ating modes ................................................................................. 109 enhanced type tm C etm (ht45f66/ht45f67) ......................................... 119 enhanced tm ope ? ation ..................................................................................................... 119 enhanced type tm registe ? desc ? iption ............................................................................ 1 ? 0 enhanced type tm ope ? ating modes ................................................................................ 1 ?? analog to digital converter C adc ........... .................................................. 141 a/d ove ? view ............. ......................................................................................................... 1 ? 1 a/d conve ? te ? data registe ? s C adrl ? adrh ................................................................... 1 ? 1 a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? adcr ? ............. ................................ 1 ?? a/d ope ? ation .................................................................................................................... 1 ?? su ?? a ? y of a/d conve ? sion steps ............. ....................................................................... 1 ?? p ? og ? a ?? ing conside ? ations ............. ................................................................................. 1 ? 6 a/d t ? ansfe ? function ............. ............................................................................................ 1 ? 6 a/d p ? og ? a ?? ing exa ? ple ................................................................................................. 1 ? 7 audio dac ........... ......................................................................................... 149 audio output and volu ? e cont ? ol ....................................................................................... 1 ? 9 voice cont ? ol ? it .................................................................................................................. 1 ? 9 digital to analog converter C dac ........... .................................................. 150 operational amplifer .................................................................................. 151 bandgap ....................................................................................................... 152 analog application circuit ........... ............................................................... 153 serial interface module C sim .................................................................... 154 spi inte ? face ...................................................................................................................... 1 ?? i ? c inte ? face ............ ............................................................................................................ 160 i ? c inte ? face ope ? ation ........................................................................................................ 160 i ? c registe ? s ....................................................................................................................... 161 spi1 interface ............................................................................................... 167 spi1 co ?? unication .......................................................................................................... 167
rev. 1.60 ? ?ove??e? ??? ?01? rev. 1.60 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu peripheral clock output ........... .................................................................. 170 pe ? iphe ? al clock ope ? ation ............. ................................................................................... 170 interrupts ...................................................................................................... 171 inte ?? upt registe ? s ............................................................................................................... 171 inte ?? upt ope ? ation ............................................................................................................. 179 exte ? nal inte ?? upt ............. .................................................................................................... 18 ? multi- function inte ?? upt ....................................................................................................... 18 ? a/d conve ? te ? inte ?? upt ...................................................................................................... 18 ? ti ? e base inte ?? upts .......................................................................................................... 183 se ? ial inte ? face module inte ?? upt ........................................................................................ 18 ? exte ? nal pe ? iphe ? al inte ?? upt ............. ................................................................................. 18 ? se ? ial pe ? iphe ? al inte ? face inte ?? upt ............. ...................................................................... 18 ? lvd inte ?? upt ....................................................................................................................... 18 ? tm inte ?? upts ....................................................................................................................... 18 ? uart inte ?? upt ............. ...................................................................................................... 18 ? inte ?? upt wake-up function ................................................................................................. 186 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 186 uart interface ............................................................................................. 187 uart exte ? nal inte ? face ..................................................................................................... 188 uart data t ? ansfe ? sche ? e .............................................................................................. 188 uart status and cont ? ol registe ? s .................................................................................... 188 baud rate gene ? ato ? .......................................................................................................... 19 ? uart setup and cont ? ol ..................................................................................................... 196 uart t ? ans ? itte ? ................................................................................................................ 197 uart receive ? ............. ...................................................................................................... 198 managing receive ? e ?? o ? s .................................................................................................. ? 00 uart inte ?? upt st ? uctu ? e ..................................................................................................... ? 01 uart powe ? down mode and wake-up ............................................................................. ? 0 ? low voltage detector C lvd .......... ............................................................. 203 lvd registe ? ............. .......................................................................................................... ? 03 lvd ope ? ation ..................................................................................................................... ? 0 ? lcd driver .................................................................................................... 205 lcd me ? o ? y ...................................................................................................................... ? 06 lcd registe ? s .................................................................................................................... ? 07 clock sou ? ce ...................................................................................................................... ? 08 lcd d ? ive ? output ............................................................................................................... ? 08 lcd wavefo ?? ti ? ing diag ? a ? s ............. ........................................................................... ? 08 p ? og ? a ?? ing conside ? ations ............. .................................................................................. ? 11 temperature sensor ... ................................................................................. 212 application circuit ....................................................................................... 213 application block diag ? a ? ............. ..................................................................................... ? 13 glucose measu ? e ci ? cuit ..................................................................................................... ? 13
rev. 1.60 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu instruction set .............................................................................................. 214 int ? oduction ......................................................................................................................... ? 1 ? inst ? uction ti ? ing ................................................................................................................ ? 1 ? moving and t ? ansfe ?? ing data ............................................................................................. ? 1 ? a ? ith ? etic ope ? ations .......................................................................................................... ? 1 ? logical and rotate ope ? ation ............................................................................................. ? 1 ? b ? anches and cont ? ol t ? ansfe ? ........................................................................................... ? 1 ? bit ope ? ations ..................................................................................................................... ? 1 ? ta ? le read ope ? ations ....................................................................................................... ? 1 ? othe ? ope ? ations ............. .................................................................................................... ? 1 ? instruction set summary .......... .................................................................. 216 ta ? le conventions ............................................................................................................... ? 16 instruction defnition ................................................................................... 218 package information ................................................................................... 227 ? 8-pin lqfp (7 ?? 7 ?? ) outline di ? ensions .................................................................. ?? 8 6 ? -pin lqfp (7 ?? 7 ?? ) outline di ? ensions .................................................................. ?? 9 80-pin lqfp (10 ?? 10 ?? ) outline di ? ensions .............................................................. ? 30
rev. 1.60 6 ?ove??e? ??? ?01? rev. 1.60 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu features cpu features ? o perating voltage f sys =4mhz: 2.2v~5.5v f sys =8mhz: 2.4v~5.5v f sys =12mhz: 2.7v~5.5v f sys =16mhz: 4.5v~5.5v ? up to 0.33s instruction cycle with 12mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? five oscillators external crystal - hxt external 32.768khz crystal - lxt external rc - erc (ht45f66/ht45f67) internal rc - hirc internal 32khz rc - lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 6 1 or 63 powerful instructions ? up to 12-level subroutine nesting ? bit man i pulation instruction peripheral features ? flash p rogram memory: 8kx16~32kx16 ? ram data memory: 256x8~512x8 ? in application programming (iap) ? watchdog t imer function ? up to 59 bidirectional i/o lines ? lcd driver function ? multiple pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output or single pulse output function ? serial interfaces module with dual spi and i 2 c interfaces ? single serial spi interface ? uart interface for fully duplex asynchronous comminucation ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? temperature sensor ? 10-bit dac ? 16-bit audio dac ? bandgap ? operational amplifer ? package types: 48-pin/64-pin and 80-pin lqfp ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years
rev. 1.60 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu general description the devices are a flash memory a/d with lcd type 8-bit high performance risc architecture microcontroller designed for applic ations that interface directly to anal og signals and which require an lcd interface. o ffering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of r am da ta me mory a s we ll a s i ap f or st orage o f n on-volatile d ata su ch a s se rial n umbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter. multiple and extremely fexible t imer modules provide timing, pulse generation and pwm generation functio ns. communication with the outside world is catered for by including fully integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protec tive fe atures such as an internal w atchdog t imer, low v oltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , lxt , erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. s election table most features are common to all devices, the main feature distinguishing them are memory capacity, i/o count, tm features, stack capacity and package types. the following table summarises the main features of each device. part no. v dd program memory data memory i/o a/d d/a audio dac t imer module interface (spi/i 2 c) spi1 uart stack package ht ?? f6 ? ? . ? v~ ? . ? v 8k 16 ?? 6 8 37 1 ? - ? it 8 10- ? it 1 16- ? it 1 10- ? it ctm ? 16- ? it stm 1 1 ? ? 8/6 ? lqfp ht ?? f66 16k 16 ? 1 ? 8 ? 9 1 ? - ? it 8 10- ? it 1 16- ? it 1 10- ? it ctm ? 16- ? it stm 1 10- ? it etm 1 1 ? 6 ? /80 lqfp ht ?? f67 3 ? k 16
rev. 1.60 8 ?ove??e? ??? ?01? rev. 1.60 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu block diagram
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rev. 1.60 10 ? ove ?? e ? ??? ? 01 ? rev. 1.60 11 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pin assignment op1o op1s0 op1s1 op1s? pa?/op1? pa6/op?o pa7/op??/i?t1 pc?/vg/i?t0 daco dacvref pc3/tx pc?/rx pe0/seg8/sda/sdi pe1/seg9/tp0_0/tp0_1 pe?/seg10/tck0 pe3/seg11/tp1_0/tp1_1 pe?/seg1?/tck1 pe?/seg13/tp?_0/tp?_1 pe6/seg1?/tck? pe7/seg1? com3 com? com1 com0 avss avdd pb ?/ a? ? pb 3/ a? 3 pd 0/ seg 0/ sck 1 pd 1/ seg 1/ scs 1b0 pd ?/ seg ?/ scs 1b1 pd 3/ seg 3/ pi?tb pd ?/ seg ?/ pck pd ?/ seg ?/ scs pd 6/ seg 6/s ck / scl pd 7/ seg 7/ sdo pa 0/ ocdsda / icpda res / ocdsck / icpck pa 1/ osc ? pa ?/ osc 1 vss pa 3/ xt 1 pa ?/ xt ? vdd c1 c? vab vc ht 45f 65/ ht 45v 65 48 lqfp -a 1 ? 3 ? ? 6 7 8 9 10 11 1? 36 3? 3? 33 3? 31 30 ?9 ?8 ?7 ?6 ?? 13 1? 1? 16 17 18 19 ?0 ?1 ?? ?3 ?? ?8 ?7 ?6 ?? ?? ?3 ?? ?1 ?0 39 38 37
rev. 1.60 10 ?ove??e? ??? ?01? rev. 1.60 11 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ht 45f 65 /ht 45v 65 64 lqfp -a pb3/a?3 pb?/a?? pb1/a?1 pb0/a?0 avdd avss op1o op1s0 op1s1 op1s? pa?/op1? pa6/op?o pa7/op??/i?t1 pc?/vg/i?t0 daco dacvref pe?/seg10/tck0 pe3/seg11/tp1_0/tp1_1 pe?/seg1?/tck1 pe?/seg13/tp?_0/tp?_1 pe6/seg1?/tck? pe7/seg1? seg16 seg17 seg18 seg19 seg?0 seg?1 seg?? seg?3 com3 com? pb ?/ advrh pb ?/ advrl pb 6/ aud pb 7/ syscko pc 0/ sdi 1 pc 1/ sdo 1 pd 0/ seg 0/ sck 1 pd 1/ seg 1/ scs 1b0 pd ?/ seg ?/ scs 1b1 pd 3/ seg 3/ pi?tb pd ?/ seg ?/ pck pd ?/ seg ?/ scs pd 6/ seg 6/s ck / scl pd 7/ seg 7/ sdo pe 0/ seg 8/ sda / sdi pe 1/ seg 9/ tp 0_0/ tp 0_1 pc 3/ tx pc ?/ rx pa 0/ ocdsda / icpda res / ocdsck / icpck pa 1/ osc ? pa ?/ o sc 1 vss pa 3/ xt 1 pa ?/ xt ? vdd c1 c? vab vc com 0 com 1 1 ? 3 ? ? 6 7 8 9 10 11 1? 13 ?0 ?1 ?? ?3 ?? ?? ?6 ?7 ?8 60616?636? ?9 30 31 3? ???3?????6?7?8?9 1? 1? 16 ?3 ?? ?? ?6 ?7 ?8 36 37 38 39 ?0 ?1 ?? 33 3? 3? 17 18 19 ?9?0?1
rev. 1.60 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 13 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ht 45f 66 ht 45f 67/ ht 45 v 67 64 lqfp -b pa1/pck/tx pc0/pi?tb/rx ocdsda/pa0/icpda ocdsck/res/icpck pc?/osc? pc1/osc1 vss pc3/xt1 pc?/xt? vdd ph6 ph1/sdi1 ph0/syscko c1 c? vab pb?/a?3 pb6/advrh pd0/seg0/tp0_0 pd1/seg1/tp0_1 pd?/seg?/tck0 pd3/seg3/tp1a pd?/seg?/tp1b_0 pd?/seg?/tp1b_1 pd6/seg6/tp1b_? pd7/seg7/tck1 pe0/seg8/tp?_0 pe1/seg9/tp?_1 pe?/seg10/tck? pe3/seg11/tp3_0 pe?/seg1?/to3_1 pe?/seg13/tck3 pa ?/ scs pa 3/ sck / scl pa ?/ sdo pa ?/ sda / sdi dacvref daco pa 6/ vg / i?t 0 pa 7/ op ??/ i?t 1 pb 1/ op 1? op 1s0 op 1o avss av dd pb ?/ a? 0 pb 3/ a? 1 pb ?/ a? ? vc com 0 com 1 com ? com 3 com ?/ seg 31 com ?/ seg 30 pg ?/ seg ?9 pg ?/ seg ?8 pg 3/ seg ?7 pg ?/ seg ?6 pg 1/ seg ?? pg 0/ seg ?? pf 7/ seg ?3 pf 6/ seg ?? pf ?/ seg ?1 1 ? 3 ? ? 6 7 8 9 10 11 1? 13 ?0 ?1 ?? ?3 ?? ?? ?6 ?7 ?8 60616?636? ?9 30 31 3? ???3?????6?7?8?9 1? 1? 16 ?3 ?? ?? ?6 ?7 ?8 36 37 38 39 ?0 ?1 ?? 33 3? 3? 17 18 19 ?9 ?0?1
rev. 1.60 1? ?ove??e? ??? ?01? rev. 1.60 13 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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rev. 1.60 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pin description HT45F65/ht45v65 pin name function opt i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb7 po ? t b pbpu st cmos pc0~pc ? po ? t c pcpu st cmos pd0~pd7 po ? t d pdpu st cmos pe0~pe7 po ? t e pepu st cmos a ? 0~a ? 3 adc input pbfs a ? pb0~pb3 advrh adc positive ? efe ? ence voltage pbfs a ? pb ? advrl adc negative ? efe ? ence voltage pbfs a ? pb ? aud audio dac output pbfs ao pb6 dacvref dac ? efe ? ence voltage a ? daco dac output ao op1o opa1 output ao op ? o opa ? output pafs ao p a6 op1 ? opa1 non-inve ? ting input pafs a ? p a ? op ?? opa ? non-inve ? ting input pafs a ? pa7 op1s0 opa1 output select 0 a ? op1s1 opa1 output select 1 a ? op1s ? opa1 output select ? a ? tck0~tck ? tm0~tm ? exte ? nal input clock st pe ?? p e ? ? pe 6 tp0_0 ? tp0_1 tm0 output st cmos pe1 ? p e1 tp1 _0 ? tp 1_1 tm1 output st cmos pe3 ? p e3 tp ? _0 ? tp ? _1 tm ? output st cmos pe ? ? pe ? i ? t0 ? i ? t1 exte ? nal inte ?? upt 0 ? 1 st p c ? ? pa7 pi ? tb pe ? iphe ? al inte ?? upt st pd3 pck pe ? iphe ? al clock output cmos p d ? sdi spi data input st pe0 sdi1 spi1 data input st pc0 sdo spi data output cmos pd7 sdo1 spi1 data output cmos pc1 scs spi slave select st cmos p d ? scs1b0 spi1 slave select 0 st cmos pd1 scs1b1 spi1 slave select 1 st cmos p d ? sck spi se ? ial clock st cmos pd6 sck1 spi1 se ? ial clock st cmos pd0 scl i ? c clock st ? mos pd6 sda i ? c data st ? mos pe0 osc1 hxt/erc pin co hxt p a ? osc ? hxt pin co hxt p a1 xt1 lxt pin co lxt p a3
rev. 1.60 1? ?ove??e? ??? ?01? rev. 1.60 1 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pin name function opt i/t o/t pin-shared mapping xt ? lxt pin co lxt p a ? ocdsck ocds clock co st icpck icp clock co st res reset input co st vdd powe ? supply pwr vss g ? ound pwr avdd adc powe ? supply pwr avss adc g ? ound pwr vg vi ? tual g ? ound a ? p c ? ocdsda ocds add ? ess/data st cmos pa0 icpda icp add ? ess/data st cmos pa0 syscko syste ? clock output cmos pb7 vab lcd voltage pu ? p vc lcd voltage pu ? p c1 ? c ? lcd voltage pu ? p seg0~7 lcd seg ? ent output cmos pd0~pd7 seg8~1 ? lcd seg ? ent output cmos pe0~pe7 seg16~ ? 3 lcd seg ? ent output cmos com0~com3 lcd co ?? on output cmos rx uart se ? ial data input pin ucr1 ucr ? st pc ? tx uart se ? ial data output pin ucr1 ucr ? cmos pc3 note: i/t: input type o/t: output type op: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output; nmos: nmos output an: analog input pin; ao: analog output pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator
rev. 1.60 16 ? ove ?? e ? ??? ? 01 ? rev. 1.60 17 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ht45f66, ht45f67/ht45v67 pin name function opt i/t o/t pin-shared mapping pa0~pa7 po ? t a pawu papu st cmos pb0~pb7 po ? t b pbpu st cmos pc0~pc ? po ? t c pcpu st cmos pd0~pd7 po ? t d pdpu st cmos pe0~pe7 po ? t e pepu st cmos pf0~pf7 po ? t f pfpu st cmos pg0~pg ? po ? t g pgpu st cmos ph0~ph6 po ? t h phpu st cmos a ? 0~a ? 3 adc input pbfs a ? pb ? ~pb ? advrh adc positive refe ? ence voltage pbfs a ? pb6 advrl adc ? egative refe ? ence voltage pbfs a ? pb7 aud audio dac output pcfs ao pc ? dacvref dac refe ? ence voltage a ? daco dac output ao op1o opa1 output ao op ? o opa ? output pbfs ao pb0 op1 ? opa1 ? on-inve ? ting input pbfs a ? pb1 op ?? opa ? ? on-inve ? ting input pafs sfs1 a ? pa7 op1s0 opa1 output select 0 a ? op1s1 opa1 output select 1 a ? op1s ? opa1 output select ? a ? tck0~tck3 tm0~tm3 exte ? nal input clock st pd ?? pd7 ? pe ?? pe ? tp0_0 ? tp0_1 tm0 output st cmos pd0 ? pd1 tp1a tm1 output st cmos pd3 tp1b_0~tp1b_ ? tm1 output st cmos pd ?? pd ?? pd6 tp ? _0 ? tp ? _1 tm ? output st cmos pe0 ? pe1 tp3_0 ? tp3_1 tm3 output st cmos pe3 ? pe ? i ? t0 ? i ? t1 exte ? nal inte ?? upt 0 ? 1 st pa6 ? pa7 pi ? tb pe ? iphe ? al inte ?? upt st pc0 pck pe ? iphe ? al clock output cmos pa1 sdi spi data input st pa ? sdi1 spi1 data input st ph1 sdo spi data output cmos pa ? sdo1 spi1 data output cmos ph ? scs spi slave select st cmos pa ? scs1b0 spi1 slave select 0 st cmos ph ? scs1b1 spi1 slave select 1 st cmos ph ? sck spi se ? ial clock st cmos pa3 sck1 spi1 se ? ial clock st cmos ph3 scl i ? c clock st ? mos pa3
rev. 1.60 16 ?ove??e? ??? ?01? rev. 1.60 17 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pin name function opt i/t o/t pin-shared mapping sda i ? c data st ? mos pa ? osc1 hxt/erc pin co hxt pc1 osc ? hxt pin co hxt pc ? xt1 lxt pin co lxt pc3 xt ? lxt pin co lxt pc ? ocdsck ocds clock co st icpck icp clock co st res reset input co st vdd powe ? supply pwr vss g ? ound pwr avdd adc powe ? supply pwr avss adc g ? ound pwr vg vi ? tual g ? ound a ? pa6 ocdsda ocds add ? ess/data st cmos pa0 icpda icp add ? ess/data st cmos pa0 syscko syste ? cclock output cmos ph0 vab lcd voltage pu ? p vc lcd voltage pu ? p c1 ? c ? lcd voltage pu ? p seg0~7 lcd seg ? ent output cmos pd0~pd7 seg8~1 ? lcd seg ? ent output cmos pe0~pe7 seg16~ ? 3 lcd seg ? ent output cmos pf0~pf7 seg ?? ~seg ? 9 lcd seg ? ent output cmos pg0~pg ? seg30 ? seg31 lcd seg ? ent output cmos com0~com ? lcd co ?? on output cmos tx uart se ? ial data output pin ucr1 ucr ? cmos pa1 rx uart se ? ial data input pin ucr1 ucr ? st pc0 note: i/t: input type o/t: output type op: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output nmos: nmos output an: analog input pin ao: analog output pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator
rev. 1.60 18 ? ove ?? e ? ??? ? 01 ? rev. 1.60 19 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 ope ? ating voltage (hxt/erc) f sys = ? mhz ? . ? ? . ? v f sys =8mhz ? . ? ? . ? v f sys =1 ? mhz ? .7 ? . ? v f sys =16mhz ? . ? ? . ? v v dd ? ope ? ating voltage (hirc) f sys = ? mhz ? . ? ? . ? v f sys =8mhz ? . ? ? . ? v f sys =1 ? mhz ? .7 ? . ? v i dd1 ope ? ating cu ?? ent (f sys =f h ? f s =f sub =f lxt o ? f lirc ) 3v ? o load ? f h = ??? khz ? adc off ? wdt ena ? le 100 1 ? 0 ? v ? 80 ?? 0 3v ? o load ? f h =1mhz ? adc off ? wdt ena ? le ?? 0 ? 00 ? v ? 00 1000 3v ? o load ? f h = ? mhz ? adc off ? wdt ena ? le ?? 0 630 ? v 700 1000 3v ? o load ? f h =8mhz ? adc off ? wdt ena ? le 0.8 1. ? ? a ? v 1. ? 3.0 ? a 3v ? o load ? f h =1 ? mhz ? adc off ? wdt ena ? le 1. ? ? . ? ? a ? v 3.0 ? .0 ? a ? v ? o load ? f h =16mhz ? adc off ? wdt ena ? le ? .0 8.0 ? a
rev. 1.60 18 ?ove??e? ??? ?01? rev. 1.60 19 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu symbol parameter test conditions min. typ. max. unit v dd conditions i dd ? ope ? ating cu ?? ent (f s =f sub =f lxt o ? f lirc ) 3v ? o load ? f h =8mhz ? f sys =f h / ?? adc off ? wdt ena ? le ? 00 7 ? 0 a ? v 800 1 ? 00 a 3v ? o load ? f h =8mhz ? f sys =f h / ?? adc off ? wdt ena ? le ?? 0 630 a ? v 700 1000 a 3v ? o load ? f h =8mhz ? f sys =f h /8 ? adc off ? wdt ena ? le ? 00 600 a ? v 600 800 a 3v ? o load ? f h =8mhz ? f sys =f h /16 ? adc off ? wdt ena ? le 360 ?? 0 a ? v ? 60 700 a 3v ? o load ? f h =8mhz ? f sys =f h /3 ?? adc off ? wdt ena ? le 3 ? 0 ? 80 a ? v ?? 0 6 ? 0 a 3v ? o load ? f h =8mhz ? f sys =f h /6 ?? adc off ? wdt ena ? le ? 80 ?? 0 a ? v ?? 0 600 a i dd3 ope ? ating cu ?? ent (lxt/lirc ? f sys =f l =f lxt ? f s =f sub =f lxt ) 3v ? o load ? adc off ? wdt ena ? le ? lvr ena ? le ? 0 70 a ? v 60 100 a i stb1 stand ? y cu ?? ent (idle) (f sys =f h ? f s =f sub =f lxt o ? f lirc ) 3v ? o load ? syste ? halt ? adc off ? wdt ena ? le ? f sys =8mhz ? spi o ? i ? c on ? pck on ? pck=f sys /8 0.3 0. ? ? a ? v 0. ? 0.8 ? a i stb ? stand ? y cu ?? ent (idle) (f sys =off ? f s =f sub =f lxt o ? f lirc ) 3v ? o load ? syste ? halt ? adc off ? wdt ena ? le 1. ? 3.0 a ? v ? . ? ? .0 a i stb3 stand ? y cu ?? ent (idle) (lxt ? f sys =f l =f lxt ? f s =f sub =f lxt ) 3v ? o load ? syste ? halt ? adc off ? wdt ena ? le ? f sys =3 ? 768hz 1.9 ? .0 a ? v 3.3 7.0 a i stb ? stand ? y cu ?? ent (sleep) (f sys =off ? f s =f sub =f lxt o ? f lirc ) 3v ? o load ? syste ? halt ? adc off ? wdt disa ? le ? f sys =1 ? mhz 0.1 1.0 a ? v 0.3 ? .0 a v il1 input low voltage fo ? i/o po ? ts 0 0.3v dd v v ih1 input high voltage fo ? i/o po ? ts 0.7v dd v dd v v il ? input low voltage ( res) 0 0. ? v dd v v ih ? input high voltage ( res) 0.9v dd v dd v v lvr1 low voltage reset voltage lvr ena ? le ? ? .1v option - ? % ? .1 + ? % v v lvr ? lvr ena ? le ? ? . ?? v option ? . ?? v v lvr3 lvr ena ? le ? 3.1 ? v option 3.1 ? v v lvr ? lvr ena ? le ? 3.8v option 3.8 v i lvr low voltage reset cu ?? ent lvr ena ? le ? lvde ? =0 30 ? 0 a v lvd1 low voltage detecto ? voltage lvde ? = 1 ? v lvd = ? .0v - ? % ? .0 + ? % v v lvd ? lvde ? = 1 ? v lvd = ? . ? v ? . ? v v lvd3 lvde ? = 1 ? v lvd = ? . ? v ? . ? v v lvd ? lvde ? = 1 ? v lvd = ? .7v ? .7 v v lvd ? lvde ? = 1 ? v lvd = 3.0v 3.0 v v lvd6 lvde ? = 1 ? v lvd = 3.3v 3.3 v v lvd7 lvde ? = 1 ? v lvd = 3.6v 3.6 v v lvd8 lvde ? = 1 ? v lvd = ? . 0v ? . 0 v i lvd1 low voltage detecto ? cu ?? ent lvr disa ? le ? lvde ? = 1 30 60 a i lvd ? lvr ena ? le ? lvde ? = 1 1 1 a i ol i/o po ? t sink cu ?? ent (pa ?? pa6 ? pa7 fo ? ht ?? f6 ? ; pa7 ? pb0 ? pb1 ? ph6 fo ? ht ?? f66/67) 3v v ol =0.1v dd 6 1 ? ? a ? v v ol =0.1v dd 10 ? 0 ? a i oh i/o po ? t sou ? ce cu ?? ent (pa ?? pa6 ? pa7 fo ? ht ?? f6 ? ; pa7 ? pb0 ? pb1 ? ph6 fo ? ht ?? f66/67) 3v v oh =0.9v dd -6 -1 ? ? a ? v v oh =0.9v dd -10 - ? 0 ? a
rev. 1.60 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu symbol parameter test conditions min. typ. max. unit v dd conditions i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd ? 8 ? a ? v v ol =0.1v dd 10 ? 0 ? a i oh i/o po ? t ? sou ? ce cu ?? ent 3v v oh =0.9v dd - ? - ? ? a ? v v oh =0.9v dd - ? -10 ? a r ph pull-high resistance of i/o po ? ts 3v ? 0 60 100 k ? v 10 30 ? 0 k a.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd condition f cpu ope ? ating clock ? . ? ~ ? . ? v dc ? mhz ? . ? ~ ? . ? v dc 8 mhz ? .7~ ? . ? v dc 1 ? mhz ? . ? ~ ? . ? v dc 16 mhz f sys syste ? clock (hxt) ? . ? ~ ? . ? v 0. ? ? mhz ? . ? ~ ? . ? v 0. ? 8 mhz ? .7~ ? . ? v 0. ? 1 ? mhz ? . ? ~ ? . ? v 0. ? 16 mhz f hirc syste ? clock (hirc) 3v/ ? v ta= ?? c - ? % ? + ? % mhz 3v/ ? v ta= ?? c - ? % 8 + ? % mhz ? v ta= ?? c - ? % 1 ? + ? % mhz ? . ? v~3.6v ta=0~70c -7% ? +7% mhz 3.0v~ ? . ? v ta=0~70c -7% ? +7% mhz ? . ? v~3.6v ta=0~70c -7% 8 +7% mhz 3.0v~ ? . ? v ta=0~70c -7% 8 +7% mhz 3.0v~ ? . ? v ta=0~70c -7% 1 ? +7% mhz f lxt syste ? clock (lxt) 3 ? 768 hz t res exte ? nal reset low pulse width 10 s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt) f sys =hxt o ? lxt 10 ?? t sys f sys =erc o ? hirc 16 f sys =lirc ? t i ? t inte ?? upt pulse width turn on rc flter 10 s t lvr low voltage width to reset 1 ? 0 ?? 0 ? 80 s t lvd low voltage width to inte ?? upt ? 0 ?? 90 s t lvds lvdo sta ? le ti ? e lvr disa ? le 1 ? 0 s lvr ena ? le 1 ? s ote: t sys i sys
rev. 1.60 ?0 ?ove??e? ??? ?01? rev. 1.60 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu adc & bandgap electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions av dd analog ope ? ating voltage ? . ? ? . ? v v adi ad input voltage 0 v ref v v ref adc input refe ? ence voltage range ? .0 av dd v v bg bandgap refe ? ence with buffe ? voltage av dd =3v -3% ? .0 +3% v t bg temperature coeffcient of build-in band gap ? efe ? ence voltage av dd =3v ? t=10~ ? 0c -30 +170 pp ? / c i bg bandgap refe ? ence with buffe ? d ? iving cu ?? ent v bg is used ? lvr disa ? le ? lvde ? =0 ? bgos[1:0]=10 ? bge ? =1 ? 00 ? 00 a i bg1 bandgap refe ? ence with buffe ? d ? iving cu ?? ent v bg is used ? lvr disa ? le ? lvde ? =0 ? bgos[1:0]=00 o ? 01 bge ? =1 ?? 0 6 ? 0 a d ? l diffe ? ential ? on-linea ? ity 3v t ad =0. ? s -3 +3 lsb i ? l integ ? al ? on-linea ? ity 3v t ad =0. ? s - ? + ? lsb i adc additional powe ? consu ? ption if a/d conve ? te ? is used 3v ? o load ? t ad =0.5s 1.0 ? .0 ? a ? v ? o load ? t ad =0.5s 1. ? 3.0 ? a t bgs v bg tu ? n on sta ? le ti ? e 10 ? s t ad a/d clock pe ? iod ? .7~ ? . ? v 0. ? 100 s t adc a/ d conve ? sion ti ? e ? .7~ ? . ? v 1 ? ? it adc 16 t ad t o ?? st adc on to adc sta ? t ? .7~ ? . ? v ? s ote: adc conersion time (t adc ) = e + dpso ph h yhu iu hd e hh h o power-on reset characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd v dd raising rate to ensu ? e powe ? -on reset 0.03 ? v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s
rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lcd d.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd condition i stb stand ? y cu ?? ent (idle) (f sys ? f wdt off ? f s =f sub =f lxt o ? f lirc ) 3v ? o load ? syste ? halt ? lcd on ? wdt off ? c type 3 6 a ? v ? 10 a i ol lcd co ?? on and seg ? ent sink cu ?? ent 3v v ol =0.1v lcd ? 10 ?? 0 a ? v 3 ? 0 700 a i oh lcd co ?? on and seg ? ent sou ? ce cu ?? ent 3v v oh =0.9v lcd -80 -160 a ? v -180 -360 a audio dac electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dac dac ope ? ating voltage ? . ? ? . ? v i dac dac ope ? ating cu ?? ent ? v 1 khz sin wave ? full-scale 3 ? . ? ? a thd total ha ?? onic disto ? tion - ?? - ? 8 d ? res resolution 16 ? it v o output voltage level 0.01 0.99 v dd 10-bit dac electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dac ope ? ating voltage ? . ? ? . ? v i ? l integ ? al ? on-linea ? ity 3v - ? + ? lsb d ? l diffe ? ential ? on-linea ? ity 3v - ? + ? lsb r o output resistance 3v ? k v os dac output voltage sta ? ility 3v bgos[1:0]=10 - ? + ? ? v v o output voltage level 0.01 0.99 v dd
rev. 1.60 ?? ?ove??e? ??? ?01? rev. 1.60 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu op amplifer electrical characteristics a c symbol parameter test conditions min. typ. max. unit v dd conditions r o output resistance ? . ? v~3.6v 7d a&?ordg . 0. ? v rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of the devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. t he p ipelining sc heme i s i mplemented i n su ch a wa y t hat i nstruction f etching a nd instruction execut ion are overlappe d, hence instructions are ef fectively executed in one cycle, with the excep tion of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. cert ain internal re gisters are im plemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to pro vide a fun ctional i/ o a nd a/ d c ontrol syst em wi th m aximum re liability a nd fe xibility. t his makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , lxt , hirc, lirc or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented a t t he be ginning of t he t 1 c lock duri ng wh ich t ime a ne w i nstruction i s fe tched. t he remaining t2~t 4 clocks carry out the decodi ng and execution functi ons. in this way , one t1~t 4 clock cyc le form s one i nstruction cyc le. al though t he fet ching and exe cution of i nstructions t akes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.60 ?? ?ove??e? ??? ?01? rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is ex - ecuted except for instructions, such as "jmp" or "call" that demand s a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. part no. program counter high byte low byte ht ?? f6 ? pc1 ? ~pc8 pcl7~pcl0 ht ?? f66 bp. ? pc1 ? ~pc8 ht ?? f67 bp.6~bp. ? note: 1. bp.5: bank pointer register bit 5 for ht45f66. 2. bp.6~bp.5: bank pointer register bit 6~bit 5 for ht45f67. program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.60 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only . the st ack i s o rganized i nto 12 l evels a nd n either p art o f t he d ata n or p art o f t he p rogram sp ace, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
part no. stack levels ht ?? f6 ? / ht ?? f66/ht ?? f67 1 ? arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.60 ?6 ?ove??e? ??? ?01? rev. 1.60 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu flash program memory the program memory is the location where the user code or program is stored. for these devices the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, these flash devices of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capacity of 8kx16 bits to 32kx16 bits. the program memory is addressed by the program counter and also contains data, tabl e informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. the program memory divided into two banks, bank 0 and bank1 for ht45f66. while the program memory di vided i nto four ba nks, ba nk 0, ba nk1, ba nk2 a nd ba nk 3 for ht 45f67. t he re quired bank is selected using bit 6 and bit 5 of the bp register. reset interrupt vector 00h 04h 3ch bank0 40h 1fffh 2000h 3fffh bank1 ht45f66 reset interrupt vector 00h 04h 3ch bank0 40h 1fffh HT45F65 reset interrupt vector 00h 04h 3ch bank0 40h 1fffh 2000h 3fffh bank1 bank2 bank3 7fffh 6000h 5fffh 4000h ht45f67 program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.60 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd [m]" or "t abrdl [m]" instructions, respectivel y. when the instruction is execut ed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "7f00h" which refers to the start address of the last page within the 32k program memory of the ht45f67. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "7f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.60 ?8 ?ove??e? ??? ?01? rev. 1.60 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a, 06h ; initialise low table pointer - note that this address mov tblp, a ; is referenced mov a, 07h ; initialise high table pointer mov tbhp, a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 7f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 7f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 7f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa0 p ? og ? a ?? ing se ? ial data/add ? ess icpck res p ? og ? a ?? ing clock and device reset vdd vdd powe ? supply vss vss g ? ound the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.
rev. 1.60 30 ? ove ?? e ? ??? ? 01 ? rev. 1.60 31 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu during the programming process, taking control of the pa0 and res pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.

note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin mcu pins data pa0 clk res in application programming C iap this device of fers iap function to update data or application program to flash rom . u sers can defne any rom location for iap , but there are some features which user must notice in using iap function. ? erase page: 32 words/page (HT45F65) erase page: 64 words/page (ht45f66/ht45f67) ? writing: 32 words/time (HT45F65) writing: 64 words/time (ht45f66/ht45f67) ? reading: 1 wod/time in application programming control register the address register, f arl/farh , and the data register , fd0l/fd0h, fd1l/fd1h, fd2l/fd2h and fd3 l/fd3h , located in da ta memory bank 0, together wi th t he c ontrol re gister , fc0 , fc 1 and fc 2, located in data memory bank 1 are the corresponding flash access registers for iap. as indirect addressing is the only way to access the fc0 and fc1 registers, all read and write operations to the registers must be performed using the indirect addressing register, iar1, and the memory pointer, mp1. because the fc0 and fc1 control registers are located at the address of 40h and 41h in data memory bank 1, the mp1 memory pointer must frst be set to the value 40/41h and the bank pointer set to "1".
rev. 1.60 30 ?ove??e? ??? ?01? rev. 1.60 31 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu fc0 register bit 7 6 5 4 3 2 1 0 ? a ? e cfwe ? fmod ? fmod1 fmod0 fwpe ? fwt frde ? frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 cfwen: confrm the fwen status 0: flash rom write disable 1: software write 1 no action when this bit is clear by frmware, the iap controller exits fwen mode. the user can read this bit to confrm the fwen status. bit 6~4 fmod2~fmod0 : mode selection. 000: write program rom 001: page erase program rom 010: reserved 011: read program rom 101: reserved 110: fwen (fash rom write enable) mode 111: reserved bit 3 fwpen : flash rom write procedure enable. 0: disabled 1: enabled when this bit is set to "1" and fmod2~fmod0 is set to 110, the program can execute "set fash write enable (fwen)". when this bit is set to "1" and fmod2~fmod0 is set to 000, the controller will move register (fd0l and fd0h) data to fash rom internal page buffer. bit 2 fwt : flash rom write control bit 0: do not initiate flash rom write or flash rom w rite process is completed. 1: initiate flash rom write process this bit can be set by software only , when write process completed, hardware will clear "fwt" bit. bit 1 frden : flash rom read enable bit 0: flash rom read disable 1: flash rom read enable bit 0 frd : flash rom read control bit 0: do not initiate flash read or flash read process is completed 1: initiate flash read process this bit can be set by software only , when read process completed, hardware will clear "frd" bit. fc1 register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~0 55h : whole chip reset when user writes 55h to this register, it will generate a reset signal to reset whole chip .
rev. 1.60 3 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 33 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu fc2 register bit 7 6 5 4 3 2 1 0 ? a ? e clwb r/w r/w por 0 bit 7 ~1 unimplemented, read as "0" bit 0 clwb : flash rom w rite buffer clear control bit 0: do not initiate clear w rite buffer or clear w rite buffer process is completed. 1: initiate clear w rite buffer process. before page write action, user must be set cl wb bit to clear w rite buf fer. this bit can be set by software only , when clear w rite buf fer process completed , hardware will clear "clwb" bit. farl register bit 7 6 5 4 3 2 1 0 ? a ? e a7 a6 a ? a ? a3 a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 a7~a0 : the fash address[7:0] farh register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e a 1 ? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~5 unimplemented, read as "0" bit 4~0 a12~a8 : the fash address [12:8] farh register (ht45f66) bit 7 6 5 4 3 2 1 0 ? a ? e a13 a 1 ? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5~0 a13~a8 : the fash address [13:8] farh register (ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e a1 ? a13 a1 ? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~0 a14~a8 : the fash address[14:8]
rev. 1.60 3? ?ove??e? ??? ?01? rev. 1.60 33 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu fd0l register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : the frst fash rom data[7:0] fd0h register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : the frst fash rom data[15:8] fd1l register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : the second fash rom data[7:0] fd1h register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : the second fash rom data[15:8] fd2l register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : the third fash rom data[7:0] fd2h register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d15~d8 : the third fash rom data[ 15:8]
rev. 1.60 3 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 3? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu fd3l register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : the fourth fash rom data[7:0] fd3h register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d15~d8 : the fourth fash rom data[ 15:8] set flash write enable (fwen) in order to allow user to change flash rom data through flash control register , the user must frst enable the flash write operation by the following procedure: ? write 110 to the fmod2~fmod0 for setting fwen mode ? set fwpen bit to 1. the step 1 and step 2 can set simultaneously ? the hardware will start a 300s counter to allow the user writing the correct pattern data to fd1l/fd1h~fd3l/fd3h. (the clock of 300s counter is from lirc.) ? once 300s counter is overfow or the pattern is uncorrect. the enable flash write operation is fail and the user must repeat the above procedure one more ? no matter, the operation is success or fail. the hardware will clear fwpen bit automatically ? the pattern data is (00h 04h 0dh 09h c3h 40h) to fd1l/fd1h~fd3l/fd3h ? once the flash write operation is enable, the user can change the flash rom data through the flash control register ? for disable the flash write operation, the user only clear cfwen, it is no need to write the above procedure set flash write enable set fmod[2:0]=110 (fwen mode) set fwpen=1, hardware set a counter wrtie the following pattern to flash data register fd1l= 00h , fd1h = 04h fd2l=0dh , fd2h = 09h fd3l=c3h , fd3h = 40h is pattern is correct ? is counter overflow ? fwpen=0 ? yes no set fwen mode fail fwpen=0 no yes set fwen mode success. yes no end set flash write enable procedure
rev. 1.60 3? ?ove??e? ??? ?01? rev. 1.60 3 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu write flash set flash write enable page erase set erase page farh & farl, set fmod[2:0]=001 set fwt=1 fwt=0 ? set fmod[2:0]=000 set address register: farh & farl wrtie data to data registers: fd0l, fd0h yes no page write finish set fwt=1 fwt = 0 set cfwen=0 end yes yes no no write finish yes no write flash program procedure
rev. 1.60 36 ? ove ?? e ? ??? ? 01 ? rev. 1.60 37 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu set frden=0 end read finish ? yes no set fmod[2:0]=011 & frden=1 flash address register: fah=xxh, fal=xxh frd=0 ? yes no read value: fd0l=xxh, fd0h=xxh set frd=1 read flash read flash program procedure
rev. 1.60 36 ?ove??e? ??? ?01? rev. 1.60 37 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? HT45F65 erase page farh farl[7:5] note 0 0000 0000 000 farl[ ? :0]: dont ca ? e. 1 0000 0000 001 ? 0000 0000 010 3 0000 0000 011 ? 0000 0000 100 ? 0000 0000 101 6 0000 0000 110 7 0000 0000 111 8 0000 0001 000 9 0000 0010 001 : : : : : : ? ht45f66 / ht45f67 erase page farh farl[7:6] note 0 0000 0000 00 farl[ ? :0]: dont ca ? e. 1 0000 0000 01 ? 0000 0000 10 3 0000 0000 11 ? 0000 0001 00 ? 0000 0001 01 6 0000 0001 10 7 0000 0001 11 8 0000 0010 00 9 0000 0010 01 : : : : : : on chip debug support (ocds) 7khuh lv an s h hpodh h hyh h s hyh do suyh an s he i he h hyh u h hyhosph suh h s d h ddo 8 hyh are dop idoo psdeoh h[hs iu s he i 8hu d h h s hyh hpodh h uhdo s hyh ehdyu e h h 6 d 6 s h +oh + hyhosph o h 6 pin h 6 dd uh ss pin oh h 6 pin h 6 o s s :h hu h h s iu he hu i are duh h 6 d 6 s in h ddo 8 hyh oo dyh hiih in h s +hyhu h 6 s are sduh h suudpp s are oo h d h od hpu suudpp s iu u puh hdoh 6 iupd refer h uuhs ph dph +oh h iu e 8 6 8hu h holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on-chip de ? ug suppo ? t clock input vdd vdd powe ? supply vss vss g ? ound
rev. 1.60 38 ? ove ?? e ? ??? ? 01 ? rev. 1.60 39 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three sections, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the devices. many of these registers can be read from and written to directly under program control, however, some remain p rotected f rom u ser m anipulation. t he se cond a rea o f da ta me mory i s r eserved f or g eneral purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory . this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. the addresses of the lcd memory area overlap those in the general purpose data memory area. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. device capacity banks ht ?? f6 ? ?? 6 8 0: 80h~ffh 1: 80h~97f ? : 80h~ffh ht ?? f66 ht ?? f67 ? 1 ? 8 0: 80h~ffh 1: 80h~9fh ? : 80h~ffh 3: 80h~ffh ? : 80h~ffh structure the da ta me mory i s subdi vided i nto se veral ba nks, a ll of whi ch a re i mplemented i n 8-bi t wi de ram. the data memory located in bank 0 is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the data memory for the device is the address 00h. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. the lcd memory is mapped into bank 1. the other banks contain only general purpose data memory for the device . as the special purpose data memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. general purpose data memory
rev. 1.60 38 ?ove??e? ??? ?01? rev. 1.60 39 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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rev. 1.60 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu special function register description most of t he spe cial func tion re gister de tails wi ll be de scribed i n t he re levant funct ional sec tion; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. di rect ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a, 04h ; setup size of block mov block, a mov a, offset adres1 ; accumulator loaded with frst ram address mov mp0, a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.60 ?0 ?ove??e? ??? ?01? rev. 1.60 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bank pointer C bp t he program and data memory are divided into several banks. selecting the required program and data me mory a rea i s a chieved usi ng t he ba nk poi nter. for ht 45f65, bi ts 1~0 of ba nk poi nter i s used to select data memory banks 0~2. for ht45f66, bits 5 of the bank pointer is used to select program memory banks 0~1, while bits 0~2 are used to select data memory banks 0~4. for ht45f67, bits 5 ~6 of the bank pointer is used to select program memory bank s 0 ~3 , while bits 0~2 are used to select data memory banks 0~ 4 . the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addressi ng the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register , care must be taken during programming. bp register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e dmbp1 dmbp0 r/w r/w r/w por 0 0 bit 7 ~2 unimplemented, read as "0" bit 1~0 dmbp1~dmbp0 : select data memory banks 00: bank0 01: bank1 10: bank2 11: undefned bp register (ht45f66) bit 7 6 5 4 3 2 1 0 ? a ? e pmbp0 dmbp ? dmbp1 dmbp0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 pmbp0: select program memory banks 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 3fffh to successfully jump to a non-consecutive program memory address located in different program memory bank using the branch instructions shcu as jmp or call, the program memory bank pointer bit, pmbp0, should frst be properly setup before the branch instructions are executed. bit 4 ~3 unimplemented, read as "0" bit 2~0 dmbp2~dmbp0 : select data memory banks 000: bank0 001: bank1 010: bank2 011: bank3 100: bank4 110~111: undefned
rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bp register (ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pmbp1 pmbp0 dmbp ? dmbp1 dmbp0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~5 pmbp1 , pmbp0 : select program memory banks 00: bank 0, program memory address is from 0000h ~ 1fffh 01: bank 1, program memory address is from 2000h ~ 3fffh 10: bank 2, program memory address is from 4000h ~ 5fffh 11: bank 3, program memory address is from 6000h ~ 7fffh to successfully jump to a non-consecutive program memory address located in different program memory bank using the branch instructions shcu as jmp or call, the corresponding program memory bank pointer bits, pmbp1~pmbp0, should frst be properly setup before the branch instructions are executed. bit 4~3 unimplemented, read as "0" bit 2 ~0 dmbp2~dmbp0 : select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 110~111: undefned accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.60 ?? ?ove??e? ??? ?01? rev. 1.60 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu status register C status this 8-bit register contains the zero fag (z) , carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 ? a ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7 ~6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero
rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are pr ovided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions are se lected t hrough t he c onfiguration o ptions. t he h igher f requency o scillators p rovide hi gher performance b ut c arry wi th i t t he d isadvantage o f h igher p ower r equirements, wh ile t he o pposite is of course true for the lower frequency osc illators. w ith the capabil ity of dynamicall y switching between fas t and s low s ystem clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? nal c ? ystal hxt ? 00khz~ ? 0mhz osc1/osc ? exte ? nal rc erc 8mhz osc1 inte ? nal high speed rc hirc ?? 8 o ? 1 ? mhz exte ? nal low speed c ? ystal lxt 3 ? .768khz xt1/xt ? inte ? nal low speed rc lirc 3 ? khz note: the external rc oscillator only exists in the ht45f66/ht45f67. oscillator types system clock confgurations there are fve methods of generating the sys tem clock, three high speed oscillators and tw o low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator , external rc oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator . the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high s peed os cillator is us ed as the s ystem os cillator is implemented us ing the h lclk bit and cks2~cks0 bits in the smod0 register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via c onfiguration opt ions. t he frequenc y of t he sl ow spe ed or hi gh spe ed syst em c lock i s a lso determined usi ng t he hl clk bit and cks2~cks0 bit s i n t he smod0 regist er. note tha t t wo oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
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note: the external rc oscillator only exists in the ht45f66/ht45f67. system clock confgurations external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe c rystal a nd a ny a ssociated re sistors a ndcapacitors a long wi th i nterconnectinglines a re a ll located as close to the mcuas possible.
? ? ? ?? ? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0pf 0pf 8mhz 0pf 0pf ? mhz 0pf 0pf 1mhz 100pf 100pf ? ote: c1 and c ? values a ? e fo ? guidance only. crystal recommended capacitor values
rev. 1.60 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu external rc oscillator C erc (ht45f66/ht45f67) using the erc oscillator only requires that a resistor , with a value between 56k and 2.4m, is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation fre quency; t he e xternal c apacitor has no i nfuence ove r t he fre quency a nd i s c onnected for stability purposes only . device trimming during the manufacturing process and the inclusion of i nternal f requency c ompensation c ircuits a re u sed t o e nsure t hat t he i nfluence o f t he p ower supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an exter nal 120k resistor connected and with a 5v voltage power supply and temperature of 25c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin p c 1, leaving pin p c 2 free for use as a normal i/o pin. for oscill ator stability and to minim ise the ef fects of noise and crosstalk, it is important to locate the capacitor and resistoras close to the mcu as possible. osc1 osc2 i/o r osc 20pf vdd external rc oscillator C erc internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as t hree fx ed f requencies o f e ither 4 mhz, 8 mhz o r 1 2mhz. de vice trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the os cillation frequency are minimis ed. as a res ult, at a power supply of either 3v or 5v a nd a t a t emperature of 25 c de grees, t he fi xed osc illation fre quency of 4mhz , 8mhz or 12mhz will have a tolerance within 1 %. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capa citor components connecte d to the 32.768khz crystal are necessary to provide oscillation. for a pplications wh ere p recise f requencies a re e ssential, t hese c omponents m ay b e r equired t o provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller activity and to conserve power . however , in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, r p , is required.
rev. 1.60 ?6 ?ove??e? ??? ?01? rev. 1.60 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe c rystal a nd a ny a ssociated re sistors a ndcapacitors a long wi th i nterconnectinglines a re a ll located as close to the mcuas possible.
?? ? ? ??? -? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .768k hz 10pf 10pf ? ote: 1. c1 and c ? values a ? e fo ? guidance only. ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 quick sta ? t 1 low-powe ? after power on , the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low- power mode.
rev. 1.60 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to three other device functions. these are the w atchdog t imer, the lcd driver and the time base interrupts. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devices have many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency f h or low frequency f l source, and is selected using the hlclk bit and cks2~cks0 bits in the smod0 register . the high speed system clock can be sourced from either an hxt , erc or hirc oscillator , selected via a configuration option. the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillator , selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the t ime base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
rev. 1.60 ?8 ?ove??e? ??? ?01? rev. 1.60 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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? ? ? ? ? ? ? - note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. together with f sys /4 it is also used as one of the clock sources for the w atchdog timer . the f tbc clock is used as a source for the t ime base interrupt functions and for the tms. the f sub is used as the lcd source. the external rc oscillator only exists in the ht45f66/ht45f67.
rev. 1.60 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f sub f s f tbc ? ormal mode on f h ~f h /6 ? on on on slow mode on f l on on/off on idle0 mode off off on on on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high spe ed oscilla tors, eit her the hxt , erc or hirc osc illators. the high spe ed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by t he cks2~c ks0 a nd hl clk bi ts i n t he smod0 re gister. al though a hi gh spe ed osc illator i s used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod0 register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. in this mode, the l vden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod0 register is low . in the sleep1 mode the cpu will be stopped. how ever the f sub and f s clocks will continue to operate if the l vden is "1" or the w atchdog t imer function is enabled and if its clock source is chosen via confguration option to come from the f sub . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod0 register is high and the fsyson bit in the smod1 register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, tms , lcd driver , spi1 and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the w atchdog t imer clock, f s , will either be on or of f dependin g upon the f s cloc k source. if the source is f sys /4 then the f s clock will be of f, and if the source comes from f sub then f s will be on.
rev. 1.60 ?0 ?ove??e? ??? ?01? rev. 1.60 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod0 register is high and the fsyson bit in the smod 1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer, tms, lcd driver , spi1 and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the w atchdog t imer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. control register a single register, smod 0 , is used for overall control of the internal clocks within the device. smod0 register bit 7 6 5 4 3 2 1 0 ? a ? e cks ? cks1 cks0 fste ? lto hto idle ? hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7 ~5 cks2~cks0 : the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temp orary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used.
rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. fast wake -up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f sub , namel y either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/ disable function is controlled using the fsten bit in the smod0 register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycle s of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases.
rev. 1.60 ?? ?ove??e? ??? ?01? rev. 1.60 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10 ?? hxt cycles 10 ?? hxt cycles 1~ ? hxt cycles 1 10 ?? hxt cycles 1~ ? f sub cycles (syste ? ? uns with f sub frst for 10 ?? hxt cycles and then switches ove ? to ? un with the hxt clock) 1~ ? hxt cycles erc 1 ? ~16 erc cycles 1 ? ~16 erc cycles 1~ ? erc cycles hirc 1 ? ~16 hirc cycles 1 ? ~16 hirc cycles 1~ ? hirc cycles lirc 1~ ? lirc cycles 1~ ? lirc cycles 1~ ? lirc cycles lxt 10 ?? ltx cycles 10 ?? ltx cycles 1~ ? lxt cycles wake-up times note that if the w atchdog t imer is disabled, which means that the lxt and lirc are all both of f, then there will be no fast w ake-up function available when the device wake-up from the sleep0 mode.

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rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod0 register while mode switching from the normal/ slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod0 register and fsyson in the smod 1 register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod0 register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod0 register.
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rev. 1.60 ?? ?ove??e? ??? ?01? rev. 1.60 ?? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "01 1", "100", "101", "1 10" or "111". a s a certain amount of time w ill be required for the high frequency clock to s tabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ? entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod0 register equal to "0" and the wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.60 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod0 register equal to "0" and the wdt or l vd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod0 register equal to "1" and the fsyson bit in smod 1 register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction, but the t ime base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod0 register equal to "1" and the fsyson bit in smod1 register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f sub clock will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.60 ?6 ?ove??e? ??? ?01? rev. 1.60 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which ha s dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the "halt" instructio n. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the instruction following the "hal t" instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.60 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu programming considerations the hxt and lxt oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is "1", the system clock can be switched to the lxt or lirc oscillator after wake up. ? there are peripheral functions, such as wdt , tms and spi1, lcd driver and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . system clock output there is a system clock output for peripheral application, please refer to control register for detail. sckc register bit 7 6 5 4 3 2 1 0 ? a ? e scke ? scks1 scks0 r/w r/w r/w r/w por 0 0 0 bit 7 scken : system clock output control 0: disabled 1: enabled bit 6~2 unimplemented, read as "0" bit 1 ~0 scks1, scks0 : system clock output selection 00: f sys 01: f sys /2 10: f sys /4 11: f sys /8
rev. 1.60 ?8 ?ove??e? ??? ?01? rev. 1.60 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lx t or lirc oscillators , again chosen via a confguration option. the w atchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variat ions. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog t imer clock source option is the f sys /4 clock. the w atchdog t imer clock source can originate from its own internal lirc oscillator , the lxt oscillator or f sys /4. it is divided by a value of 2 8 to 2 18 , using the ws2~ws0 bits in the wdtc register to obtain the required w atchdog t imer time-out period. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 ? a ? e we ? we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7 ~3 we4~we0 : wdt enable 10101: disable 01010: enable (default) other values: mcu reset (reset will be active after 2~3 lirc clock for debounce time) if the mcu reset caused we4 ~ we0 in wdtc software reset, the wrf flag of smod1 register will be set. bit 2~0 ws2~ws0 : select wdt timeout period 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s (default) 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s
rev. 1.60 60 ? ove ?? e ? ??? ? 01 ? rev. 1.60 61 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the clear watchdog instructions. under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the second is using the w atchdog t imer software clear instructions and the third is via a hal t instruction. to c lear t he w atchdog t imer i s t o use t he si ngle "cl r w dt" i nstruction. a si mple e xecution of "clr wdt" will clear the wdt .

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? ??? watchdog timer smod1 register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 fsyson : f sys control in idle mode 0 : disable 1 : enable bit 6~3 unimplemented, read as "0" bit 2 lvrf : reset caused by lvr function activation 0: not active 1: active this bit can be clear to "0", but can not set to "1". bit 1 lrf : reset caused by lvrc setting 0: not active 1: active this bit can be clear to "0", but can not set to "1". bit 0 wrf : reset caused by we[4:0] setting 0: not active 1: active this bit can be clear to "0", but can not set to "1".
rev. 1.60 60 ?ove??e? ??? ?01? rev. 1.60 61 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power -on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been appli ed and the mi crocontroller is al ready runni ng, the res li ne is forc efully pull ed low . in such a c ase, k nown a s a n ormal o peration r eset, so me o f t he r egisters r emain u nchanged a llowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the w atchdog t imer overfows and resets. all types of reset operations result in dif ferent register condition s being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a reset can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. power-on reset timing chart res pin as the reset pin is shared with pc.0 , the reset function must be selected using a confguration option. although the has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabili se quickly at power -on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the will be inhibited. after the res line reache s a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the will begin normal operation. t he abbreviation sst in the fgures stands for system start-up t imer.
rev. 1.60 6 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 63 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu for most applicati ons a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. external res circuit note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using exter nal hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. res reset timing chart low voltage reset C lvr the mi crocontroller cont ains a low volt age reset circui t in order to moni tor the supply volt age of the de vice, whi ch is selected vi a a confguration option. if the suppl y voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device intern ally. the l vr includes the following specifcations: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristic s. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected using confguration options. low voltage reset timing chart
rev. 1.60 6? ?ove??e? ??? ?01? rev. 1.60 63 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? lvrc register bit 7 6 5 4 3 2 1 0 ? a ? e lvs7 lvs6 lvs ? lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~0 lvs7 ~ lvs0 : lvr voltage select 01010101: 2.1v (default) 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: mcu reset (reset will be active after 2~3 lirc clock for debounce time). when an actual low voltage condition occurs, as specifed by one of the four defned lvr v oltage v alues a bove, a n mc u r eset wi ll b e generated. i n t his si tuation t he register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ? smod1 register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 x unknown bit 7 fsyson : f sys control in idle mode described elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf : reset caused by lvr function activation 0: not active 1: active this bit can be clear to "0", but can not set to "1". bit 1 lrf : reset caused by lvrc setting 0: not active 1: active this bit can be clear to "0", but can not set to "1". bit 0 wrf : reset caused by we[4:0] setting described elsewhere.
rev. 1.60 6 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 6? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to "1". wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset condition s 0 0 powe ? -on ? eset u u res o ? lvr ? eset du ? ing ? o ?? al o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing ? o ?? al o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep m ode ope ? ation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upt s all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins counting ti ? e ? /event counte ? ti ? e ? counte ? will ? e tu ? ned off input/output po ? t s i/o po ? ts will ? e setup as inputs stack pointe ? stack pointe ? will point to the top of the stack
rev. 1.60 6? ?ove??e? ??? ?01? rev. 1.60 6 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. HT45F65 register name power on reset external or lvr reset wdt reset from normal operation state wdt reset from halt state iar0 ---- ---- ---- ---- ---- ---- ---- ---- mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ---- ---- mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- --00 ---- --00 ---- --00 ---- --uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu smod0 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu i ? teg ---- 0000 ---- 0000 ---- 0000 ---- uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu i ? tc0 -000 0000 000 0000 000 0000 -uuu uuuu i ? tc1 -000 -000 -000 -000 -000 -000 -uuu -uuu i ? tc ? --00 --00 --00 --00 --00 --00 --uu -uu sckc 0--- --00 0--- --00 0--- --00 u--- --00 mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 -000 0000 -000 0000 -000 0000 -uuu uuuu mfi ? 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu ---0 0000 ---0 0000 ---0 0000 ---u uuuu pc ---1 1111 ---1 1111 ---1 1111 ---u uuuu pcc ---1 1111 ---1 1111 ---1 1111 ---u uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pafs 000- ---- 000- ---- 000- ---- uuu- ----
rev. 1.60 66 ? ove ?? e ? ??? ? 01 ? rev. 1.60 67 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register name power on reset external or lvr reset wdt reset from normal operation state wdt reset from halt state pbfs 0000 0000 0000 0000 0000 0000 uuuu uuuu pcfs ---00 0000 ---00 0000 ---00 0000 ---u uuuu pdfs0 -000 0000 -000 0000 -000 0000 -uuu uuuu pdfs1 ---0 0000 ---0 0000 ---0 0000 ---u uuuu pefs0 -000 0000 -000 0000 -000 0000 -uuu uuuu pefs1 ---0 0000 ---0 0000 ---0 0000 ---u uuuu pres ---- ---0 ---- ---0 ---- ---0 ---- ---u smod1 0--- -x00 0--- -x00 0--- -x00 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- uuuu ---- usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txrrxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr0 011- -000 011- -000 011- -000 uuu- -uuu adcr1 ---- -000 ---- -000 ---- -000 ---- -uuu adcr ? ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 0000 1110 0000 1110 0000 uuuu uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu lcdc 000- ---0 000- ---0 000- ---0 uuu- ---u spi1c0 111- 0-00 111- 0-00 111- 0-00 uuu- u-uu spi1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu spi1d 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 66 ?ove??e? ??? ?01? rev. 1.60 67 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register name power on reset external or lvr reset wdt reset from normal operation state wdt reset from halt state adac 000- ---0 000- ---0 000- ---0 uuu- uuuu adal 0000 ---- 0000 ---- 0000 ---- uuuu ---- adah 0000 0000 0000 0000 0000 0000 uuuu uuuu bgc ---0 --00 ---0 --00 ---0 --00 ---u --uu dac ---- ---0 ---- ---0 ---- ---0 ---- ---u dal 00-- ---- 00-- ---- 00-- ---- uu-- ---- dah 0000 0000 0000 0000 0000 0000 0000 0000 tsc 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu pvref 0000 0000 0000 0000 0000 0000 uuuu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh ---0 0000 ---0 0000 ---0 0000 ---u uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3h 0000 0000 0000 0000 0000 0000 uuuu uuuu opc1 0000 0000 0000 0000 0000 0000 uuuu uuuu opc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented ht45f66 register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) iar0 ---- ---- ---- ---- ---- ---- ---- ---- mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ---- ---- mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp --0- --00 --0- --00 --0- --00 --u- --uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu smod0 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu i ? teg ---- 0000 ---- 0000 ---- 0000 ---- uuuu wdtc 0101 0011 0101 0011 0101 0011 u uuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu
rev. 1.60 68 ? ove ?? e ? ??? ? 01 ? rev. 1.60 69 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) i ? tc0 -000 0000 -000 0000 -000 0000 -uuu uuuu i ? tc1 0000 0000 0000 0000 0000 0000 uuuu uuuu i ? tc ? --00 --00 --00 --00 --00 --00 --uu --uu sckc 0--- --00 0--- --00 0--- --00 u--- --00 mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi ? 0000 0000 0000 0000 0000 0000 u uuu uuuu mfi3 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu --00 0000 --00 0000 --00 0000 --uu uuuu pc --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --uu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pgpu --00 0000 --00 0000 --00 0000 --uu uuuu pg --11 1111 --11 1111 --11 1111 --uu uuuu pgc --11 1111 --11 1111 --11 1111 --uu uuuu phpu -000 0000 -000 0000 -000 0000 -uuu uuuu ph -111 1111 -111 1111 -111 1111 -uuu uuuu phc -111 1111 -111 1111 -111 1111 -uuu uuuu pafs 00-- ---- 00-- ---- 00-- ---- uu-- ---- pbfs 0000 0000 0000 0000 0000 0000 uuuu uuuu pcfs --0- ---- --0- ---- --0- ---- --u- ---- pdfs 0000 0000 0000 0000 0000 0000 uuuu uuuu pefs 0000 0000 0000 0000 0000 0000 uuuu uuuu pffs 0000 0000 0000 0000 0000 0000 uuuu uuuu pgfs --00 0000 --00 0000 --00 0000 --uu uuuu phfs ---- ---0 ---- ---0 ---- ---0 ---- ---u sfs0 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 68 ?ove??e? ??? ?01? rev. 1.60 69 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) sfs1 0000 0000 0000 0000 0000 0000 uuuu uuuu smod1 0--- -x00 0--- -x00 0--- -x00 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 u uuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- uuuu ---- usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr0 011- -000 011- -000 011- -000 uuu- -uuu adcr1 ---- -000 ---- -000 ---- -000 ---- -uuu adcr ? ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 0000 1110 0000 1110 0000 uuuu uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c ? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh ---- --00 ---- --00 ---- --00 ---- --uu tm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 70 ? ove ?? e ? ??? ? 01 ? rev. 1.60 71 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu lcdc 000- ---0 000- ---0 000- ---0 uuu- ---u spi1c0 1110 0000 1110 0000 1110 0000 uuuu uuuu spi1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu spi1d 0000 0000 0000 0000 0000 0000 uuuu uuuu adac 000- ---0 000- ---0 000- ---0 uuu- uuuu adal 0000 ---- 0000 ---- 0000 ---- uuuu ---- adah 0000 0000 0000 0000 0000 0000 uuuu uuuu bgc ---0 --00 ---0 --00 ---0 --00 ---u --uu dac ---- ---0 ---- ---0 ---- ---0 ---- ---u dal 00-- ---- 00-- ---- 00-- ---- uu-- ---- dah 0000 0000 0000 0000 0000 0000 0000 0000 tsc 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh --00 0000 --00 0000 --00 0000 --uu uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3h 0000 0000 0000 0000 0000 0000 uuuu uuuu pvref 0000 0000 0000 0000 0000 0000 uuuu uuuu opc1 0000 0000 0000 0000 0000 0000 uuuu uuuu opc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu fc0 0000 0000 0000 0000 0000 0000 uuuu uuuu fc1 0000 0000 0000 0000 0000 0000 uuuu uuuu fc ? ---- ---0 ---- ---0 ---- ---0 ---- ---u note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.60 70 ?ove??e? ??? ?01? rev. 1.60 71 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ht45f67 register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) iar0 ---- ---- ---- ---- ---- ---- ---- ---- mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu iar1 ---- ---- ---- ---- ---- ---- ---- ---- mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp -00- -000 -00- -000 -00- -000 -uu- -uuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu smod0 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu i ? teg ---- 0000 ---- 0000 ---- 0000 ---- uuuu wdtc 0101 0011 0101 0011 0101 0011 u uuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu i ? tc0 -000 0000 -000 0000 -000 0000 -uuu uuuu i ? tc1 0000 0000 0000 0000 0000 0000 uuuu uuuu i ? tc ? --00 --00 --00 --00 --00 --00 --uu --uu sckc 0--- --00 0--- --00 0--- --00 u--- --00 mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi ? 0000 0000 0000 0000 0000 0000 u uuu uuuu mfi3 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu --00 0000 --00 0000 --00 0000 --uu uuuu pc --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --uu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 7 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 73 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pgpu --00 0000 --00 0000 --00 0000 --uu uuuu pg --11 1111 --11 1111 --11 1111 --uu uuuu pgc --11 1111 --11 1111 --11 1111 --uu uuuu phpu -000 0000 -000 0000 -000 0000 -uuu uuuu ph -111 1111 -111 1111 -111 1111 -uuu uuuu phc -111 1111 -111 1111 -111 1111 -uuu uuuu pafs 00-- ---- 00-- ---- 00-- ---- uu-- ---- pbfs 0000 0000 0000 0000 0000 0000 uuuu uuuu pcfs --0- ---- --0- ---- --0- ---- --u- ---- pdfs 0000 0000 0000 0000 0000 0000 uuuu uuuu pefs 0000 0000 0000 0000 0000 0000 uuuu uuuu pffs 0000 0000 0000 0000 0000 0000 uuuu uuuu pgfs --00 0000 --00 0000 --00 0000 --uu uuuu phfs ---- ---0 ---- ---0 ---- ---0 ---- ---u sfs0 0000 0000 0000 0000 0000 0000 uuuu uuuu sfs1 0000 0000 0000 0000 0000 0000 uuuu uuuu smod1 0--- -x00 0--- -x00 0--- -x00 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 u uuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- uuuu ---- usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr0 011- -000 011- -000 011- -000 uuu- -uuu adcr1 ---- -000 ---- -000 ---- -000 ---- -uuu adcr ? ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 0000 1110 0000 1110 0000 uuuu uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 7? ?ove??e? ??? ?01? rev. 1.60 73 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c ? 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh ---- --00 ---- --00 ---- --00 ---- --uu tm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu lcdc 000- ---0 000- ---0 000- ---0 uuu- ---u spi1c0 1110 0000 1110 0000 1110 0000 uuuu uuuu spi1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu spi1d 0000 0000 0000 0000 0000 0000 uuuu uuuu adac 000- ---0 000- ---0 000- ---0 uuu- uuuu adal 0000 ---- 0000 ---- 0000 ---- uuuu ---- adah 0000 0000 0000 0000 0000 0000 uuuu uuuu bgc ---0 --00 ---0 --00 ---0 --00 ---u --uu dac ---- ---0 ---- ---0 ---- ---0 ---- ---u dal 00-- ---- 00-- ---- 00-- ---- uu-- ---- dah 0000 0000 0000 0000 0000 0000 0000 0000 tsc 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh -000 0000 -000 0000 -000 0000 -0uu uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd ? h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3l 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 7 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 7? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu register power on reset res or lvr reset wdt time-out (normal operation) wdt time-out (halt) fd3h 0000 0000 0000 0000 0000 0000 uuuu uuuu pvref 0000 0000 0000 0000 0000 0000 uuuu uuuu opc1 0000 0000 0000 0000 0000 0000 uuuu uuuu opc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu fc0 0000 0000 0000 0000 0000 0000 uuuu uuuu fc1 0000 0000 0000 0000 0000 0000 uuuu uuuu fc ? ---- ---0 ---- ---0 ---- ---0 ---- ---u note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vices pro vide bi directional i nput/output l ines l abeled wi th por t na mes p a~ph . t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ? HT45F65 register name bit 7 6 5 4 3 2 1 0 pawu pawu 7 pawu 6 pawu ? pawu ? pawu 3 pawu ? pawu 1 pawu 0 papu papu 7 papu 6 papu ? papu ? papu 3 papu ? papu 1 papu 0 pa pa7 pa6 pa ? pa ? pa3 pa ? pa1 pa0 pac pac 7 pac 6 pac ? pac ? pac 3 pac ? pac 1 pac 0 pbpu pbpu7 pbpu6 pbpu ? pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 pb pb7 pb6 pb ? pb ? pb3 pb ? pb1 pb0 pbc pbc7 pbc6 pbc ? pbc ? pbc3 pbc ? pbc1 pbc0 pcpu pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 pc pc ? pc3 pc ? pc1 pc0 pcc pcc ? pcc3 pcc ? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu ? pdpu ? pdpu3 pdpu ? pdpu1 pdpu0 pd pd7 pd6 pd ? pd ? pd3 pd ? pd1 pd0 pdc pdc7 pdc6 pdc ? pdc ? pdc3 pdc ? pdc1 pdc0 pepu pepu7 pepu6 pepu ? pepu ? pepu3 pepu ? pepu1 pepu0 pe pe7 pe6 pe ? pe ? pe3 pe ? pe1 pe0 pec pec7 pec6 pec ? pec ? pec3 pec ? pec1 pec0
rev. 1.60 7? ?ove??e? ??? ?01? rev. 1.60 7 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? ht45f66/ht45f67 register name bit 7 6 5 4 3 2 1 0 pawu pawu 7 pawu 6 pawu ? pawu ? pawu 3 pawu ? pawu 1 pawu 0 papu papu 7 papu 6 papu ? papu ? papu 3 papu ? papu 1 papu 0 pa pa7 pa6 pa ? pa ? pa3 pa ? pa1 pa0 pac pac 7 pac 6 pac ? pac ? pac 3 pac ? pac 1 pac 0 pbpu pbpu7 pbpu6 pbpu ? pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 pb pb7 pb6 pb ? pb ? pb3 pb ? pb1 pb0 pbc pbc7 pbc6 pbc ? pbc ? pbc3 pbc ? pbc1 pbc0 pcpu pcpu ? pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 pc pc ? pc ? pc3 pc ? pc1 pc0 pcc pcc ? pcc ? pcc3 pcc ? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu ? pdpu ? pdpu3 pdpu ? pdpu1 pdpu0 pd pd7 pd6 pd ? pd ? pd3 pd ? pd1 pd0 pdc pdc7 pdc6 pdc ? pdc ? pdc3 pdc ? pdc1 pdc0 pepu pepu7 pepu6 pepu ? pepu ? pepu3 pepu ? pepu1 pepu0 pe pe7 pe6 pe ? pe ? pe3 pe ? pe1 pe0 pec pec7 pec6 pec ? pec ? pec3 pec ? pec1 pec0 pfpu pfpu7 pfpu6 pfpu ? pfpu ? pfpu3 pfpu ? pfpu1 pfpu0 pf pf7 pf6 pf ? pf ? pf3 pf ? pf1 pf0 pfc pfc7 pfc6 pfc ? pfc ? pfc3 pfc ? pfc1 pfc0 pgpu pgpu ? pgpu ? pgpu3 pgpu ? pgpu1 pgpu0 pg pg ? pg ? pg3 pg ? pg1 pg0 pgc pgc ? pgc ? pgc3 pgc ? pgc1 pgc0 phpu phpu6 phpu ? phpu ? phpu3 phpu ? phpu1 phpu0 ph ph6 ph ? ph ? ph3 ph ? ph1 ph0 phc phc6 phc ? phc ? phc3 phc ? phc1 phc0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p apu~phpu, a nd a re i mplemented usi ng we ak pmos transistors. pa pu register bit 7 6 5 4 3 2 1 0 ? a ? e papu 7 papu 6 papu ? papu ? papu 3 papu ? papu 1 papu 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register bit 7 6 5 4 3 2 1 0 ? a ? e pbpu7 pbpu6 pbpu ? pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0
rev. 1.60 76 ? ove ?? e ? ??? ? 01 ? rev. 1.60 77 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pcpu register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 pcpu register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pcpu ? pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 pdpu register bit 7 6 5 4 3 2 1 0 ? a ? e pdpu7 pdpu6 pdpu ? pdpu ? pdpu3 pdpu ? pdpu1 pdpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pepu register bit 7 6 5 4 3 2 1 0 ? a ? e pepu7 pepu6 pepu ? pepu ? pepu3 pepu ? pepu1 pepu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pfpu register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pfpu7 pfpu6 pfpu ? pfpu ? pfpu3 pfpu ? pfpu1 pfpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pgpu register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pgpu ? pgpu ? pgpu3 pgpu ? pgpu1 pgpu0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 phpu register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e phpu6 phpu ? phpu ? phpu3 phpu ? phpu1 phpu0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~0 papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun/phpun : i/o port pull- high control 0: disable 1: enable
rev. 1.60 76 ?ove??e? ??? ?01? rev. 1.60 77 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pa wu register bit 7 6 5 4 3 2 1 0 ? a ? e pawu 7 pawu 6 pawu ? pawu ? pawu 3 pawu ? pawu 1 pawu 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~0 pa wu7 ~pawu0 : port a bit 7~bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its ow n control register known as p ac~phc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 ? a ? e pac 7 pac 6 pac ? pac ? pac 3 pac ? pac 1 pac 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register bit 7 6 5 4 3 2 1 0 ? a ? e pbc7 pbc6 pbc ? pbc ? pbc3 pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pcc ? pcc3 pcc ? pcc1 pcc0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1
rev. 1.60 78 ? ove ?? e ? ??? ? 01 ? rev. 1.60 79 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pcc register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pcc ? pcc ? pcc3 pcc ? pcc1 pcc0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 pdc register bit 7 6 5 4 3 2 1 0 ? a ? e pdc7 pdc6 pdc ? pdc ? pdc3 pdc ? pdc1 pdc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pec register bit 7 6 5 4 3 2 1 0 ? a ? e pec7 pec6 pec ? pec ? pec3 pec ? pec1 pec0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pfc register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pfc7 pfc6 pfc ? pfc ? pfc3 pfc ? pfc1 pfc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pgc register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pgc ? pgc ? pgc3 pgc ? pgc1 pgc0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 phc register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e phc6 phc ? phc ? phc3 phc ? phc1 phc0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 bit 7 unimplemented, read as "0" bit 6~0 pacn/pbcn/pccn /pdcn/pecn/pfcn/pgcn/phcn : i/o port input/output control 0: output 1: input
rev. 1.60 78 ?ove??e? ??? ?01? rev. 1.60 79 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established where more than one pin function is selected simultaneously . additionally there are a se ries o f p afs, pb fs, pc fs, pdfs, pe fs, pffs, pgfs, phfs, sfs0 a nd sfs1 r egisters t o establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device include s p afs, pbfs, pcfs, pdfs, pefs, pffs, pgfs, phfs, sfs0 and sfs1 registers which can select the functions of certain pins . pin-remapping register list (HT45F65) register name bit 7 6 5 4 3 2 1 0 pafs pafs7 pafs6 pafs ? pbfs pbfs7 pbfs6 pbfs ? pbfs ? pbfs3 pbfs ? pbfs1 pbfs0 pcfs pcfs ? pcfs3 pcfs ? pcfs1 pcfs0 pdfs0 pdfs ? pdfs3 pdfs ?? pdfs ? 1 pdfs1 ? pdfs1 1 pdfs00 pdfs1 pdfs7 pdfs 6 ? pdfs61 pdfs ?? pdfs ? 1 pefs0 pefs 3 ? pefs31 pefs ? pefs 1 ? pefs11 pefs 0 ? pefs01 pefs1 pefs7 pefs6 pefs ? ? pefs ? 1 pefs ? pin-remapping register list (ht45f66/ht45f67) register name bit 7 6 5 4 3 2 1 0 pafs pafs7 pafs6 pbfs pbfs7 pbfs6 pbfs ? pbfs ? pbfs3 pbfs ? pbfs1 pbfs0 pcfs pcfs ? pcfs ? pcfs3 pcfs ? pcfs1 pcfs0 pdfs pdfs7 pdfs6 pdfs ? pdfs ? pdfs3 pdfs ? pdfs1 pdfs0 pefs pefs7 pefs6 pefs ? pefs ? pefs3 pefs ? pefs1 pefs0 pffs pffs7 pffs6 pffs ? pffs pffs3 pffs ? pffs1 pffs0 pgfs pgfs ? pgfs ? pgfs3 pgfs ? pgfs1 pgfs0 phfs phfs0 sfs0 sfs07 sfs06 sfs0 ? sfs0 ? sfs03 sfs0 ? sfs01 sfs00 sfs1 sfs17 sfs16 sfs1 ? sfs1 ? sfs13 sfs1 ? sfs11 sfs10
rev. 1.60 80 ? ove ?? e ? ??? ? 01 ? rev. 1.60 81 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pafs register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pafs7 pafs6 pafs ? r/w r/w r/w r/w por 0 0 0 bit 7 pafs7 : port a7 function selection 0: i/o 1: op2n bit 6 pafs6 : port a6 function selection 0: i/o 1: op2o bit 5 pafs 5 : port a 5 function selection 0: i/o 1: op1n bit 4~0 unimplemented, read as "0" pafs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pafs7 pafs6 r/w r/w r/w por 0 0 bit 7 pafs7 : port a7 function selection 0 : i/o 1 : special function (op2n or int 1) bit 6 pafs6 : port a6 function selection 0: i/o 1: special function (vg or int 0) bit 5~0 unimplemented, read as "0"
rev. 1.60 80 ?ove??e? ??? ?01? rev. 1.60 81 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pbfs register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pbfs7 pbfs6 pbfs ? pbfs ? pbfs3 pbfs ? pbfs1 pbfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pbfs7 : port b7 function selection 0: i/o 1: syscko bit 6 pbfs6 : port b6 function selection 0: i/o 1: aud bit 5 pbfs5 : port b5 function selection 0: i/o 1: advrl bit 4 pbfs4 : port b4 function selection 0: i/o 1: advrh bit 3 pbfs3 : port b3 function selection 0: i/o 1: an3 bit 2 pbfs2 : port b2 function selection 0: i/o 1: an2 bit 1 pbfs1 : port b1 function selection 0: i/o 1: an1 bit 0 pbfs0 : port b0 function selection 0: i/o 1: an0 pbfs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pbfs7 pbfs6 pbfs ? pbfs ? pbfs3 pbfs ? pbfs1 pbfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pbfs7 : port b 7 function selection 0 : i/o 1 : advrl bit 6 pbfs6 : port b6 function selection 0: i/o 1: advrh bit 5 pbfs5 : port b5 function selection 0: i/o 1: an3 bit 4 pbfs4 : port b4 function selection 0: i/o 1: an2 bit 3 pbfs3 : port b3 function selection 0: i/o 1: an1 bit 2 pbfs2 : port b2 function selection 0: i/o 1: an0
rev. 1.60 8 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 83 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 1 pbfs1 : port b1 function selection 0: i/o 1: op1n bit 0 pbfs0 : port b0 function selection 0: i/o 1: op2o pcfs register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pcfs ? pcfs3 pcfs ? pcfs1 pcfs0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4 pcfs4 : port c4 function selection 0: i/o 1: vg bit 3 pcfs3 : port c3 function selection 0: i/o 1: tx bit 2 pcfs2 : port c2 function selection 0: i/o 1: rx bit 1 pcfs1 : port c1 function selection 0: i/o 1: sdo1 bit 0 pcfs0 : port c0 function selection 0: i/o 1: sdi1 pcfs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pcfs ? pcfs ? pcfs3 pcfs ? pcfs1 pcfs0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pcfs5 : port c5 function selection 0: i/o 1: aud bit 4 pcfs4 : port c4 function selection 0: i/o 1: by confguration option bit 3 pcfs3 : port c3 function selection 0: i/o 1: by confguration option bit 2 pcfs2 : port c2 function selection 0: i/o 1: by confguration option bit 1 pcfs1 : port c1 function selection 0: i/o 1: by confguration option bit 0 pcfs0 : port c0 function selection 0: i/o 1: by confguration option
rev. 1.60 8? ?ove??e? ??? ?01? rev. 1.60 83 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pdfs0 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pdfs ? pdfs3 pdfs ?? pdfs ? 1 pdfs1 ? pdfs1 1 pdfs00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 pdfs4 : port d4 function selection 0: i/o 1: seg4 bit 5 pdfs3 : port d3 function selection 0: i/o 1: seg3 bit 4~3 pdfs22~ pdfs21 : port d2 function selection 00: i/o 01: seg2 others: i/o bit 2~1 pdfs12~ pdfs11 : port d1 function selection 00: i/o 01: seg1 others: i/o bit 0 pdfs00 : port d0 function selection 0: i/o 1: seg0 pdfs1 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pdfs7 pdfs 6 ? pdfs61 pdfs ?? pdfs ? 1 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4 pdfs7 : port d7 function selection 0: i/o 1: seg7 bit 3~2 pdfs62~ pdfs61 : port d6 function selection 00: i/o 01: seg6 others: i/o bit 1~0 pdfs52~ pdfs51 : port d5 function selection 00: i/o 01: seg5 others: i/o
rev. 1.60 8 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 8? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pdfs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pdfs7 pdfs6 pdfs ? pdfs ? pdfs3 pdfs ? pdfs1 pdfs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pdfs7 : port d 7 function selection 0 : i/o 1 : special function (seg7 or tck1 ) this bit setting does not affect the tck1 function. bit 6 pdfs6 : port d6 function selection 0: i/o 1: special function (seg6 or tp1b_2) bit 5 pdfs5 : port d5 function selection 0: i/o 1: special function (seg5 or tp1b_1) bit 4 pdfs4 : port d4 function selection 0: i/o 1: special function (seg4 or tp1b_0) bit 3 pdfs3 : port d3 function selection 0: i/o 1: special function (seg3 or tp1a) bit 2 pdfs2 : port d2 function selection 0: i/o 1: special function (seg2 or tck0) bit 1 pdfs1 : port d1 function selection 0: i/o 1: special function (seg1 or tp0_1) bit 0 pdfs0 : port d0 function selection 0: i/o 1: special function (seg0 or tp0_0) pefs0 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pefs 3 ? pefs31 pefs ? pefs 1 ? pefs11 pefs 0 ? pefs01 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~5 pefs32~ pefs31 : port e3 function selection 00: i/o 01: seg11 others: tp1_0 or tp1_1 bit 4 pefs2 : port e2 function selection 0: i/o 1: seg10 bit 3~2 pefs12~ pefs11 : port e1 function selection 00: i/o 01: seg9 others: tp0_0 or tp0_1 bit 1~0 pefs02~ pefs01 : port e0 function selection 00: i/o 01: seg8 others: i/o
rev. 1.60 8? ?ove??e? ??? ?01? rev. 1.60 8 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pefs1 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e pefs7 pefs6 pefs ? ? pefs ? 1 pefs ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4 pefs7 : port e7 function selection 0: i/o 1: seg15 bit 3 pefs6 : port e6 function selection 0: i/o 1: seg14 bit 2~1 pefs52~ pefs51 : port e5 function selection 00: i/o 01: seg13 others: tp2_0 or tp2_1 bit 0 pefs4 : port e4 function selection 0: i/o 1: seg12 pefs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pefs7 pefs6 pefs ? pefs ? pefs3 pefs ? pefs1 pefs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pefs7 : port e7 function selection 0: i/o 1: seg15 bit 6 pefs6 : port e6 function selection 0: i/o 1: seg14 bit 5 pefs5 : port e5 function selection 0: i/o 1: special function (seg13 or tck3) bit 4 pefs4 : port e4 function selection 0: i/o 1: special function (seg12 or tp3_1) bit 3 pefs3 : port e3 function selection 0: i/o 1: special function (seg11 or tp3_0) bit 2 pefs2 : port e2 function selection 0: i/o 1: special function (seg10 or tck2) bit 1 pefs1 : port e1 function selection 0: i/o 1: special function (seg9 or tp2_1) bit 0 pefs0 : port e0 function selection 0: i/o 1: special function (seg8 or tp2_0)
rev. 1.60 86 ? ove ?? e ? ??? ? 01 ? rev. 1.60 87 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pffs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pffs7 pffs6 pffs ? pffs pffs3 pffs ? pffs1 pffs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pffs7 : port f7 function selection 0: i/o 1: seg23 bit 6 pffs6 : port f6 function selection 0: i/o 1: seg22 bit 5 pffs5 : port f5 function selection 0: i/o 1: seg21 bit 4 pffs4 : port f4 function selection 0: i/o 1: seg20 bit 3 pffs3 : port f3 function selection 0: i/o 1: seg19 bit 2 pffs2 : port f2 function selection 0: i/o 1: seg18 bit 1 pffs1 : port f1 function selection 0: i/o 1: seg17 bit 0 pffs0 : port f0 function selection 0: i/o 1: seg16
rev. 1.60 86 ?ove??e? ??? ?01? rev. 1.60 87 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pgfs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e pgfs ? pgfs ? pgfs3 pgfs ? pgfs1 pgfs0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 pgfs5 : port g5 function selection 0: i/o 1: seg29 bit 4 pgfs4 : port g4 function selection 0: i/o 1: seg28 bit 3 pgfs3 : port g3 function selection 0: i/o 1: seg27 bit 2 pgfs2 : port g2 function selection 0: i/o 1: seg26 bit 1 pgfs1 : port g1 function selection 0: i/o 1: seg25 bit 0 pgfs0 : port g0 function selection 0: i/o 1: seg24 phfs register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e phfs0 r/w r/w por 0 bit 7 ~1 unimplemented, read as "0" bit 0 phfs0 : port g0 function selection 0: i/o 1: syscko
rev. 1.60 88 ? ove ?? e ? ??? ? 01 ? rev. 1.60 89 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu sfs0 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e sfs07 sfs06 sfs0 ? sfs0 ? sfs03 sfs0 ? sfs01 sfs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sfs07 : pd7 special function selection 0: seg7 1: tck1 (input) when pd7 is set to normal i/o input mode (pdc7=1 & pdfs7=0), it is recommended to disable tm1 to avoid to obtain wrong clock source. bit 6 sfs06 : pd6 special function selection 0: seg6 1: tp1b_2 bit 5 sfs05 : pd5 special function selection 0: seg5 1: tp1b_1 bit 4 sfs04 : pd4 special function selection 0: seg4 1: tp1b_0 bit 3 sfs03 : pd3 special function selection 0: seg3 1: tp1a bit 2 sfs02 : pd2 special function selection 0: seg2 1: tck0 (input) when pd2 is set to normal i/o input mode (pdc2=1 & pdfs2=0), it is recommended to disable tm0 to avoid to obtain wrong clock source. bit 1 sfs01 : pd1 special function selection 0: seg1 1: tp0_1 bit 0 sfs00 : pd0 special function selection 0: seg0 1: tp0_0
rev. 1.60 88 ?ove??e? ??? ?01? rev. 1.60 89 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu sfs1 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e sfs17 sfs16 sfs1 ? sfs1 ? sfs13 sfs1 ? sfs11 sfs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 sfs17 : pa7 special function selection 0: op2n 1: int1 (input) when p a7 i s set t o norm al i/o i nput m ode, i t i s recom mended t o disable int1 t o avoid to obtain wrong clock source. bit 6 sfs16 : pa6 special function selection 0: vg 1: int0 (input) when p a6 i s set t o norm al i/o i nput m ode, i t i s recom mended t o disable int0 t o avoid to obtain wrong clock source. bit 5 sfs15 : pe5 special function selection 0: seg13 1: tck3 (input) when pe5 is set to normal i/o input mode (pec5=1 & pefs5=0), it is recommended to disable tm3 to avoid to obtain wrong clock source. bit 4 sfs14 : pe4 special function selection 0: seg12 1: tp3_1 bit 3 sfs13 : pe3 special function selection 0: seg11 1: tp3_0 bit 2 sfs12 : pe2 special function selection 0: seg10 1: tck2 (input) when pe2 is set to normal i/o input mode (pec2=1 & pefs2=0), it is recommended to disable tm2 to avoid to obtain wrong clock source. bit 1 sfs11 : pe1 special function selection 0: seg9 1: tp2_1 bit 0 sfs10 : pe0 special function selection 0: seg8 1: tp2_0
rev. 1.60 90 ? ove ?? e ? ??? ? 01 ? rev. 1.60 91 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

?? ? ?? ? ? ? generic input/output structure programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~phc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, p a~ph, a re frst progra mmed. se lecting whi ch pi ns a re i nputs a nd whi ch a re outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions . n ote that w hen us ing thes e bit control instructions , a read-modify-w rite operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.60 90 ?ove??e? ??? ?01? rev. 1.60 91 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two o r t hree i ndividual i nterrupts. t he a ddition o f i nput a nd o utput p ins f or e ach t m e nsures t hat users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain four tms with each tm having a reference name of tm0, tm1, tm2 and tm3. each individual tm can be categori sed as a certain type, namely compact t ype tm, standard t ype tm or enhanced t ype tm. although similar in nature, the dif ferent tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and dif ferences between the three types of tms are summarised in the accompanying table. function ctm stm etm ti ? e ? /counte ? i/p captu ? e co ? pa ? e match output pwm channels 1 1 ? single pulse output 1 ? pwm align ? ent edge edge edge & cent ? e pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod duty o ? pe ? iod tm function summary this chip contains a specifc number of either compact t ype, standard t ype and enhanced t ype tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 ht ?? f6 ? 10- ? it ctm 10- ? it ctm 16- ? it stm ht ?? f66 / ht ?? f6 7 10- ? it ctm 10- ? it etm 16- ? it stm 10- ? it ctm tm name/type reference tm operation the three dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.60 9 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 93 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setti ng these bits to the value 101 will selec t a reserved clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. all tm output pin names have a "_n" suffx. pin names that include a "_1" or "_2" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm ht ?? f6 ? tp0_0 ? tp0_1 tp1 _0 ? tp 1_1 tp ? _0 ? tp ? _1 ht ?? f66 /ht ?? f67 tp0_0 ? tp0_1 tp3_0 ? tp3_1 tp ? _0 ? tp ? _1 tp1a ? tp1b_0 ? tp1b_1 ? tp1b_ ? tm output pins
rev. 1.60 9? ?ove??e? ??? ?01? rev. 1.60 93 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10- bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.

the following steps show the read and write procedures: ? writing data to ccrb or ccra ? step 1. w rite data to low byte tmxal or tmxbl C n ote that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the "mov" instruction to acces s the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values.
rev. 1.60 9 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 9? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the c ompact t m c an a lso b e c ontrolled wi th a n e xternal i nput p in a nd c an d rive t wo e xternal o utput pins. these two external output pins can be the same signal or the inverse signal. device name tm no. tm input pin tm output pin ht ?? f6 ? 10- ? it ctm 0 ? 1 tck0 ? tck 1 tp0_0 ? tp0_1 ; tp1 _0 ? tp 1_1 ht ?? f66 / ht ?? f67 10- ? it ctm 0 ? 3 tck0 ? tck3 tp0_0 ? tp0_1 ; tp3_0 ? tp3_1 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram (for HT45F65, n=0 or 1; for ht45f66/ht45f67, n=0 or 3)
rev. 1.60 9? ?ove??e? ??? ?01? rev. 1.60 9 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu compact type tm register description overall operat ion of t he compa ct tm i s c ontrolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d ? d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d ? d ? d3 d ? d1 d0 tmnah d9 d8 compact tm register list tmnc0 register bit 7 6 5 4 3 2 1 0 ? a ? e tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the cl ock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high.
rev. 1.60 96 ? ove ?? e ? ??? ? 01 ? rev. 1.60 97 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 ? a ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1, tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1, tnio0 : select tp n _0, tp n _1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/ c ounter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.60 96 ?ove??e? ??? ?01? rev. 1.60 97 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin change s sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch hi gh, switch low or to toggl e its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state , it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when t he tm is running. bit 3 tnoc : tp n _0, tp n _1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tp n _0, tp n _1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp n _0 or tp n _1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.60 98 ? ove ?? e ? ??? ? 01 ? rev. 1.60 99 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tmndl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~ 2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~ 2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8
rev. 1.60 98 ?ove??e? ??? ?01? rev. 1.60 99 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.60 100 ? ove ?? e ? ??? ? 01 ? rev. 1.60 101 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high compare match output mode C tncclr= 0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.60 100 ?ove??e? ??? ?01? rev. 1.60 101 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change compare match output mode C tncclr = 1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.60 10 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 103 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? ctm, pwm mode, edge-aligned mode, t ndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b p e ? iod 1 ? 8 ?? 6 38 ? ? 1 ? 6 ? 0 768 896 10 ?? duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra = 128, the ctm pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? ctm, pwm mode, edge-aligned mode, t ndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b p e ? iod ccra duty 1 ? 8 ?? 6 38 ? ? 1 ? 6 ? 0 768 896 10 ?? the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.60 10? ?ove??e? ??? ?01? rev. 1.60 103 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( tnoc =0) pwm mode C tndpx = 0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 10 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 10? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccra pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccrp pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tm o / p pin ( tnoc =0) pwm mode C tndpx = 1 note: 1. here tndpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 10? ?ove??e? ??? ?01? rev. 1.60 10 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive two external output pins. device name tm no. tm input pin tm output pin ht ?? f6 ? 16 - ? it stm ? tck ? tp ? _0 ? tp ? _1 ht ?? f66/ht ?? f67 16 - ? it stm ? tck ? tp ? _0 ? tp ? _1 standard tm operation there i s a 16 -bit wi de st m. at t he c ore i s a 16- bit c ount-up c ounter whi ch i s dri ven by a use r selectable internal or external clock source. there are also two internal comparators with the names, comparator a a nd c omparator p . t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th ccrp and ccra registers. the ccrp comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the ccra is the sixteen bits and therefore compares all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear the counter by changing the t2on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
? ? ? ? ? ? ? ? ? ? ? ? ? -?? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ? ? ? ? ?? ? ?- standard type tm block digram
rev. 1.60 106 ? ove ?? e ? ??? ? 01 ? rev. 1.60 107 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the eight ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm ? c0 t ? pau t ? ck ? t ? ck1 t ? ck0 t ? o ? tm ? c1 t ? m1 t ? m0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr tm ? dl d7 d6 d ? d ? d3 d ? d1 d0 tm ? dh d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 tm ? al d7 d6 d ? d ? d3 d ? d1 d0 tm ? ah d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 tm ? rp d7 d6 d ? d ? d3 d ? d1 d0 16-bit standard tm register list tm2c0 register bit 7 6 5 4 3 2 1 0 ? a ? e t ? pau t ? ck ? t ? ck1 t ? ck0 t ? o ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0 : select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the cl ock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value w ill be res et to zero, however when the bit changes from high to low , the internal counter will
rev. 1.60 106 ?ove??e? ??? ?01? rev. 1.60 107 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as "0" tm2c1 register bit 7 6 5 4 3 2 1 0 ? a ? e t ? m1 t ? m0 t ? io1 t ? io0 t ? oc t ? pol t ? dpx t ? cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1, t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t2m1 and t2m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1, t2io0 : select tp 2 _0, tp 2 _1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/ c ounter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t 2io1 a nd t 2io0 bi ts de termine how t he tm out put pin change s sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch hi gh, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register . note that the output level requested by the t2io1 and t2io0 bits must be dif ferent from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the t2io1 and t2io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t 2io1 and t 2io0 bits are changed when the tm is running.
rev. 1.60 108 ? ove ?? e ? ??? ? 01 ? rev. 1.60 109 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t2dpx : tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm2 counter clear condition 0: tm2 comparatror p match 1: tm2 comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm mode , single pulse or input capture mode. tm2dl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tm 2 counter low byte register bit 7 ~ bit 0 tm2 1 6 -bit counter bit 7 ~ bit 0 tm2dh register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~0 d15~d8 : tm 2 counter high byte register bit 7 ~ bit 0 tm2 1 6 -bit counter bit 15 ~ bit 8
rev. 1.60 108 ?ove??e? ??? ?01? rev. 1.60 109 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tm2al register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tm 2 ccra low byte register bit 7 ~ bit 0 tm2 1 6 -bit ccra bit 7 ~ bit 0 tm2ah register bit 7 6 5 4 3 2 1 0 ? a ? e d1 ? d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~~ 0 d15~d8 : tm 2 ccra high byte register bit 7 ~ bit 0 tm2 1 6 -bit ccra bit 15 ~ bit 8 tm2rp register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tm2 ccrp register bit 7 ~ bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15 ~ bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256(1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 2cclr bi t i s se t t o zero. set ting t he t 2cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o overfl ow a t i ts maximum value. standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t2m1 and t2m0 bits in the tm2c1 register. compare output mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t2cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t 2af a nd t 2pf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated.
rev. 1.60 110 ? ove ?? e ? ??? ? 01 ? rev. 1.60 111 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu if the t2cclr bit in the tm2c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t2af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t2cclr i s h igh n o t 2pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an t2af interrupt request fag is generated after a compare match occurs from comparator a. the t2pf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t2io1 and t2io0 bits in the tm2c1 register . the tm output pin can be selected using the t2io1 and t2io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t2on bit changes from low to high, is setup using the t2oc bit. note that if the t2io1 and t2io0 bits are zero then no pin change will take place. ccra ccrp 0 xffffh counte? ove?flow ccra int . flag tnaf ccrp int . flag tnpf ccrp > 0 counte? clea?ed ?y ccrp value tm o/ p pin tno? pause counte? reset output pin set to initial level low if tnoc = 0 output toggle with tnaf flag he?e tnio [1:0 ] = 11 toggle output select ?ow tnio [1:0] = 10 active high output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it tncclr = 0 ; tnm [1:0 ] = 00 tnpau resu?e stop ti?e ccrp > 0 ccrp = 0 tnapol output pin reset to initial value output inve?ts when tnpol is high output cont?olled ?y othe? pin - sha?ed function counte? value compare match output mode C tncclr = 0 (n=2) note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to itsinitial state by a tnon bit rising edge
rev. 1.60 110 ?ove??e? ??? ?01? rev. 1.60 111 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ccrp ccra 0 xffff ccra = 0 counte? ove?flows ccrp int . flag tnpf ccra int . flag tnaf ccra > 0 counte? clea?ed ?y ccra value tm o / p pin tno? pause counte? reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag he?e tnio [1:0 ] = 11 toggle output select ?ow tnio [1:0 ] = 10 active high output select tnpau resu?e stop ti?e tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change ccra = 0 output inve?ts when tnpol is high tnpol tncclr = 1 ; tnm [1:0] = 00 output cont?olled ?y othe? pin - sha?ed function output not affected ?y tnaf flag ?e?ains high until ?eset ?y tno? ?it counte? value compare match output mode C tncclr = 1 (n=2) note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
rev. 1.60 11 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 113 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu timer/counter mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t 2m1 and t 2m0 i n t he t m2c1 regi ster should be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 2cclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t2dpx bit in the tm2c1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t2oc bit in the tm2c1 register is used to select the required polarity of the pwm waveform while the two t2io1 and t2io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t2pol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm mode, edge-aligned mode, t 2dpx=0 ccrp 1~255 000b pe ? iod ccrp ?? 6 6 ?? 36 duty ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 2 and ccra = 128, the stm pwm output frequency = (f sys /4)/(2256) = f sys /2048 = 7.8125khz, duty = 128/(2256) = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stm, pwm mode, edge-aligned mode, t 2dpx=1 ccrp 1~255 000b pe ? iod ccra duty ccrp ?? 6 6 ?? 36 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 000b.
rev. 1.60 11 ? ?ove??e? ??? ?01? rev. 1.60 113 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( tnoc =0) pwm mode C tndpx = 0 (n=2) note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 11 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 11 ? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccra pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccrp pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tm o / p pin ( tnoc =0) pwm mode C tndpx = 1 (n=2) note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 11 ? ?ove??e? ??? ?01? rev. 1.60 11 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu single pulse mode to se lect t his mode , bit s t 2m1 and t 2m0 i n t he t m2c1 regi ster should be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t2on bit, which can be implemented using the application program. however in the single pulse mode, the t2on bit can also be made to automatically change from low to high using the external tck2 pin, which will in turn initiate the single pulse output. when the t2on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t2on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t2on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.

? ? ? ? ? ?? ? ? ?? single pulse generation (n=2) however a compare match from comparator a will also automatically clear the t2on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t2on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t2cclr and t2dpx bits are not used in this mode.
rev. 1.60 116 ? ove ?? e ? ??? ? 01 ? rev. 1.60 117 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tno? ?etu?ns high tnm [1:0 ] = 10 ; tnio [1:0 ] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 ?o ccrp inte??upts gene?ated tm o / p pin ( tnoc =0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?atch tckn pin t?igge? auto . set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode (n=2) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit hight 5. in the single pulse mode, tnio [1:0] must be set to "11" and can not be changed.
rev. 1.60 116 ?ove??e? ??? ?01? rev. 1.60 117 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu capture input mode to s elect this mode bits t2m1 and t2m0 in the tm 2c1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tp2_0 or tp2_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t2io1 and t2io0 bits in the tm 2c1 regis ter. the counter is s tarted w hen the t2o n bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp2_0 or tp2_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp2_0 or tp2_1 pin the counter will continue to free run until the t2on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of ov erflow i nterrupt si gnals fro m t he cc rp c an be a use ful m ethod i n m easuring l ong pulse widths. the t2io1 and t2io0 bits can select the active trigger edge on the tp2_0 or tp2_1 pin to be a ris ing edge, falling edge or both edge types . if the t2io 1 and t2io 0 bits are both s et high, then no capture operation will take place irrespective of what happens on the tp2_0 or tp2_1 pin, however it must be noted that the counter will continue to run. as the tp2_0 or tp2_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t2cclr and t2dpx bits are not used in this mode.
rev. 1.60 118 ? ove ?? e ? ??? ? 01 ? rev. 1.60 119 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value yy ccrp tno? tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value ti?e counte? clea?ed ?y ccrp pause resu?e counte? reset tnm [1:0 ] = 01 tm captu?e pin tpn _x xx counte? stop tnio [1:0 ] value xx yy xx yy active edge active edge active edge 00 ? rising edge 01 ? falling edge 10 ? both edges 11 ? disa?le captu?e capture input mode (n=2) note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.60 118 ?ove??e? ??? ?01? rev. 1.60 119 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu enhanced type tm C etm (ht45f66/ht45f67) the enhanced t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. device name tm no. tm input pin tm output pin ht ?? f66/ht ?? f67 10 - ? it etm 1 tck1 tp 1a ? tp1b _0 ? tp1b_1 ? tp1b_ ? enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock s ource. there are three internal comparators w ith the names, comparator a , comparator b and comparator p . these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
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? ? ? ? ? ? enhanced type tm block diagram (n=1)
rev. 1.60 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1o ? t1rp ? t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1 cd ? t1cclr tm1c ? t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d ? d ? d3 d ? d1 d0 tm1dh d9 d8 tm1al d7 d6 d ? d ? d3 d ? d1 d0 tm1ah d9 d8 tm1bl d7 d6 d ? d ? d3 d ? d1 d0 tm1bh d9 d8 10-bit enhanced tm register list tm1c0 register bit 7 6 5 4 3 2 1 0 ? a ? e t1pau t1ck ? t1ck1 t1ck0 t1o ? t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selectin g the reserved clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falling edge . the cl ock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption.
rev. 1.60 1?0 ?ove??e? ??? ?01? rev. 1.60 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu when the bit changes state from low to high the internal counter value w ill be res et to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tm1c1 register bit 7 6 5 4 3 2 1 0 ? a ? e t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cd ? t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1, t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm shoul d be switched of f before any changes are made to the t1am1 and t1am0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1, t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/ c ounter mode unused
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register . note that the output level requested by the t1aio1 and t1aio0 bits must be dif ferent from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state , it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running. bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter . remember that the e nhanced t m c ontains t hree c omparators, com parator a, com parator b a nd comparator p , but only comparator a or comparator p can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implement ed if the ccrp bits are all cleared to zero. the t1cclr bit is not us ed in the s ingle p ulse or input capture mode.
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tm1c2 register bit 7 6 5 4 3 2 1 0 ? a ? e t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1, t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the t m sh ould b e swi tched o ff b efore a ny c hanges a re m ade t o t he t 1bm1 a nd t1bm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1, t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register . note that the output level re quested by t he t 1bio1 a nd t 1bio0 bi ts m ust be di fferent from t he i nitial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state , it can be reset to its initial level by changing the level of the t1on bit from low to high. in t he pwm mode , t he t 1bio1 a nd t 1bio0 bi ts de termine how t he t m out put pi n changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he value of t he t 1bio1 a nd t 1bio0 bi ts only a fter t he t m ha s be en swi tched of f. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running.
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1~0 t1pwm1, t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tm1 counter low byte register bit 7 ~ bit 0 tm1 10-bit counter bit 7 ~ bit 0 tm1dh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~ 2 unimplemented, read as "0" bit 1~0 d9~d8 : tm1 counter high byte register bit 1 ~ bit 0 tm1 10-bit counter bit 9 ~ bit 8 tm1al register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tm1 ccra low byte register bit 7 ~ bit 0 tm1 10-bit ccra bit 7 ~ bit 0
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tm1ah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tm1 ccra high byte register bit 1 ~ bit 0 tm1 10-bit ccra bit 9 ~ bit 8 tm1bl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : tm1 ccr b low byte register bit 7 ~ bit 0 tm1 10-bit ccr b bit 7 ~ bit 0 tm1bh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~ 2 unimplemented, read as "0" bit 1~0 d9~d8 : tm1 ccr b high byte register bit 1 ~ bit 0 tm1 10-bit ccr b bit 9 ~ bit 8 enhanced type tm operating modes the enhanced t ype tm can operat e in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t1am1 and t1am0 bits in the tm1c1, and the t1bm1 and t1bm0 bits in the tm1c2 register. etm operating mode ccra compare match output mode ccra timer/counter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb co ? pa ? e match output mode ccrb ti ? e ? /counte ? mode ccrb pwm output mode ccrb single pulse output mode ccrb input captu ? e mode "": permitted "": not pe ?? itted
rev. 1.60 1 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu compare output mode to select this mode, bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1 and tm1c2 registers should be all clear ed to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p . when the t1cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow. here both the t1af and t1pf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the t1cclr bit in the tm1c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t1af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t1cclr is high no t1pf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t1af or t1bf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the t1pf interrupt request flag, generated from a compare match from comparator p , will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the t1aio1 and t1aio0 bits in the tm1c1 register for etm ccra, and the t1bio1 and t1bio0 bits in the tm1c2 register for etm ccrb. the tm output pin can be selected using the t1aio1, t1aio0 bits (for the tp1a pin) and t1bio1, t1bio0 bits (for the tp1b_0, tp1b_1 or tp1b_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparat or b. the initial condition of the tm output pin, which is setup after the t1on bit changes from low to high, is setup using the t1aoc or t1boc bit for tp1a or tp1b_0, tp1b_1, tp1b_2 output pins. note that if the t1aio1, t1aio0 and t1bio1, t1bio0 bits are zero then no pin change will take place.
rev. 1.60 1?6 ?ove??e? ??? ?01? rev. 1.60 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrp ccra tno? tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o /p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnam [1:0 ] = 00 output pin set to initial level low if tnaoc =0 output toggle with tnaf flag ?ote tnaio [1:0 ] = 10 active high output select he?e tnaio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnapol is high etm ccra compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.60 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrp ccrb tno? tnpau tnbpol ccrp int . flag tnpf ccrb int . flag tnbf tpnb o /p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnbm [1:0 ] = 00 output pin set to initial level low if tnboc =0 output toggle with tnbf flag ?ote tnbio [1:0 ] = 10 active high output select he?e tnbio [1:0 ] = 11 toggle output select output not affected ?y tnbf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnbpol is high etm ccrb compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.60 1?8 ?ove??e? ??? ?01? rev. 1.60 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrp ccra tno? tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o /p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnam [1:0 ] = 00 output pin set to initial level low if tnaoc =0 output toggle with tnaf flag ?ote tnaio [1:0 ] = 10 active high output select he?e tnaio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnapol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change etm ccra compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.60 130 ? ove ?? e ? ??? ? 01 ? rev. 1.60 131 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value 0x3 ff ccrb ccra tno? tnpau tnbpol ccrb int . flag tnbf ccra int . flag tnaf tpnb o /p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnbm [1:0 ] = 00 output pin set to initial level low if tnboc =0 output toggle with tnbf flag ?ote tnbio [1:0 ] = 10 active high output select he?e tnbio [1:0 ] = 11 toggle output select output not affected ?y tnbf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnbpol is high ?o tnaf flag gene?ated on ccra ove?flow etm ccrb compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 timer/counter mode to select this mode, bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1 and tm1c2 register should be set to 1 1 respectively . the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. t he exception is that in the t imer/ counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function.
rev. 1.60 130 ?ove??e? ??? ?01? rev. 1.60 131 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu pwm output mode to select this mode, bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1 and tm1c2 register should be set to 10 respectively and also the corresponding t1aio1, t1aio0 and t1bio1, t1bio0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 1cclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t1dpx bit in the tm1c1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t1oc bit in the tm1c1 register is used to select the required polarity of the pwm waveform while the two t1io1 and t1io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t1pol bit is used to reverse the polarity of the pwm output waveform. ? etm, pwm mode, edge - aligned mode, t1cclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b p e ? iod 1 ? 8 ?? 6 38 ? ? 1 ? 6 ? 0 768 896 10 ?? a duty ccra b duty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. ? etm, pwm mode, edge - aligned mode, t1cclr=1 ccrp 1 2 3 511 512 1021 1022 1023 p e ? iod 1 ? 3 ? 11 ? 1 ? 10 ? 1 10 ?? 10 ? 3 b duty ccrb ? etm, pwm mode, center - aligned mode, t1cclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ?? 6 38 ? ? 1 ? 6 ? 0 768 896 10 ?? ? 0 ? 6 a duty (ccra ? )-1 b duty (ccrb ? )-1 ? etm, pwm mode, center - aligned mode, t1cclr=1 ccrp 1 2 3 511 512 1021 1022 1023 p e ? iod ? 3 ? 11 ? 1 ? 10 ? 1 10 ?? 10 ? 3 ? 0 ? 6 b duty (ccrb ? )-1
rev. 1.60 13 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 133 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc =1) ti?e counte? clea?ed ?y ccrp pause resu?e stop counte? resta?t tncclr = 0; tnam [1:0 ] = 10? tnbm [1:0 ] = 10; tnpwm [1:0 ] = 00 output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) duty cycle set ?y ccra duty cycle set ?y ccrb pwm pe?iod set ?y ccrp duty cycle set ?y ccra duty cycle set ?y ccra etm pwm mode C edge aligned (n=1) note: 1. here tncclr=0 therefore ccrp clears counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty
rev. 1.60 13? ?ove??e? ??? ?01? rev. 1.60 133 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccra tno? tnpau tnbpol ccrb int . flag tnbf ti?e counte? clea?ed ?y ccra pause resu?e stop counte? resta?t tncclr = 1 ; tnbm [1:0 ] = 10; tnpwm [1:0 ] = 00 output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnbpol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) duty cycle set ?y ccrb pwm pe?iod set ?y ccra etm pwm mode C edge aligned (n=1) note: 1. here tncclr=1, therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin.
rev. 1.60 13 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 13? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrp ccra tno? tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc =1) ti?e pause resu?e stop counte? resta?t tncclr = 0; tnam [1:0 ] = 10? tnbm [1:0 ] = 10; tnpwm [1:0 ] = 11 output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) duty cycle set ?y ccra duty cycle set ?y ccrb pwm pe?iod set ?y ccrp etm pwm mode - centre aligned (n=1) note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.60 13? ?ove??e? ??? ?01? rev. 1.60 13 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccra tno? tnpau tnbpol ccra int . flag tnaf ccrb int . flag tnbf ti?e pause resu?e stop counte? resta?t tncclr = 1 ; tnbm [1:0 ] = 10; tnpwm [1:0 ] = 11 output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function ccrb tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) duty cycle set ?y ccrb pwm pe?iod set ?y ccra output inve?ts when tnbpol is high ccrp int . flag tnpf etm pwm mode C centre aligned (n=1) note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.60 136 ? ove ?? e ? ??? ? 01 ? rev. 1.60 137 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu single pulse mode to select this mode, the required bit pairs, t1am1, t1am0 and t1bm1, t1bm0 should be set to 10 respectively and also the corresponding t1aio1, t1aio0 and t1bio1, t1bio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tp1a output leading edge is a low to high transition of the t1on bit, which can be implemented using the application program. the trigger for the pulse tp1b output leading edge i s a c ompare m atch fr om c omparator b , wh ich c an b e i mplemented u sing t he a pplication program. howe ver i n t he si ngle pul se mod e, t he t 1on bi t c an a lso be m ade t o a utomatically change from low to high using the external tck1 pin, whi ch will in turn init iate the singl e pulse output of tp1a. when the t1on bit transitions to a high level, the counter will start running and the pulse leading edge of tp1a will be generated. the t1on bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tp1a and tp1b will be generated when the t1on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the t1on bit and thus generate the single pulse output trailing edge of tp1a and tp1b. in this way the ccra value can be u sed t o c ontrol t he p ulse wi dth o f t p1a. t he c cra-ccrb v alue c an b e u sed t o c ontrol t he pulse widt h of t p1b. a c ompare m atch from com parator a a nd com parator b wil l a lso ge nerate tm inter rupts. the counter can only be reset back to zero when the t1on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t1cclr bit is also not used.

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rev. 1.60 136 ?ove??e? ??? ?01? rev. 1.60 137 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu counte? value ccrb ccra tno? tnpau tnapol ccrb int. flag tnbf ccra int. flag tnaf tpna pin ( tnaoc =1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tno? ?etu?ns high tnam [1:0 ] = 10 ? tnbm [1:0 ] = 10 ; tnaio [1:0 ] = 11 ? tnbio [1:0 ] = 11 pulse width set ?y ( ccra -ccrb ) output inve?ts when tnbpol =1 tckn pin softwa?e t?igge? clea?ed ?y ccra ?atch tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnbpol tpna pin ( tnaoc =0) tpnb pin ( tnboc =1) tpnb pin ( tnboc =0) pulse width set ?y ccra output inve?ts when tnapol =1 single pulse mode (n=1) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to "1 1" and can not be changed.
rev. 1.60 138 ? ove ?? e ? ??? ? 01 ? rev. 1.60 139 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu capture input mode to select this mode , bits t1am1, t1am0 and t1bm1, t1bm0 in the tm1c1 and tm1c2 registers should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tp1a and tp1b_0, tp1b_1, tp1b_2 pins, whose a ctive e dge c an b e e ither a r ising e dge, a f alling e dge o r b oth r ising a nd f alling e dges; t he active edge transition type is selecte d using the t1aio1, t1aio0 and t1bio1, t1bio0 bits in the tm1c1 and tm1c2 registers. the counter is started when the t1on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp 1a and tp 1b_0, tp 1b_1, tp 1b_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tp1a and tp1b_0, tp1b_1, tp1b_2 pi ns the counter will continue to free run until the t1on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the t1aio1, t1aio0 and t1bio1, t1bio0 bi ts c an se lect t he a ctive t rigger e dge on t he t p1a a nd t p1b_0, t p1b_1, t p1b_2 pi ns to be a rising edge, falling edge or both edge types. if the t1aio1, t1aio0 and t1bio1, t1bio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp1a and tp1b_0, tp1b_1, tp1b_2 pins, however it must be noted that the counter will continue to run. as the tp1a and tp1b_0, tp1b_1, tp1b_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transition s on this pin may cause an input capture operation to be executed. the t1cclr, t1aoc, t1boc, t1apol and t1bpol bits are not used in this mode.
rev. 1.60 138 ?ove??e? ??? ?01? rev. 1.60 139 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ccrp counte? ove?flow ccrp int. flag tnpf ccra int. flag tnaf tno? ?it pause counte? reset tnpau ?it resu?e stop ti?e yy xx ccra value xx tm captu?e pin yy tnaio1? tnaio0 value 00 - rising edge 01 - falling edge 11 - disa?le captu?e active edge active edge xx 10 - both edges active edges yy tnam1? tnam0 = 01 counte? value etm ccra capture input mode (n=1) note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnaoc and tnapol bits not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.60 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ccrp counte? ove?flow ccrp int. flag tnpf ccrb int. flag tnbf tno? ?it pause counte? reset tnpau ?it resu?e stop yy xx ccrb value xx tm captu?e pin yy tnbio1? tnbio0 value 00 - rising edge 01 - falling edge 11 - disa?le captu?e active edge active edge xx 10 - both edges active edges yy tnbm1? tnbm0 = 01 ti?e counte? value etm ccrb capture input mode (n=1) note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function C tnboc and tnbpol bits not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.60 1?0 ?ove??e? ??? ?01? rev. 1.60 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu analog to digital converter C adc the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter, channel 0~3 are for external signal input, channel 4~6 are for opa1 application and channel 7 is for opa2 application. the positive reference voltage is selected by vrps[1:0] option, and the negative reference voltage is selected by vrns[1:0]. device input channels a/d channel select bits input pins ht ?? f6 ? /ht ?? f66/ht ?? f67 8 acs ? ~acs0 a?0~an7 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers.

? ? ? ? ? ?? -??? ? ? ? ? ? ? ? a/d converter structure a/d converter data registers C adrl, adrh the device, whic h has an int ernal 12-bi t a/d conv erter, requires two dat a regi sters, a hig h byt e register, known as adrh, an d a lo w byt e regi ster, kno wn as adrl. afte r th e con version pro cess takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion val ue. onl y the hig h byt e regi ster, adrh, uti lises it s full 8-bi t cont ents. the low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl d3 d ? d1 d0 adrh d11 d10 d9 d8 d7 d6 d ? d ? a/d data registers
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu adrl, adrh register bit adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ? a ? e d11 d10 d9 d8 d7 d6 d ? d ? d3 d ? d1 d0 r/w r r r r r r r r r r r r por x x x x x x x x x x x x "x" unknown "" unimplemented, read as "0" d11~d0 : adc conversion data a/d converter control registers C adcr0, adcr1, adcr 2 to control the function and operation of the a/d converter , three control registers known as adcr0, adcr1 a nd adc r2 a re p rovided. t hese 8 -bit r egisters defne f unctions such a s t he se lection o f wh ich analog channel is connected to the internal a/d converter , the digitised data format, the a/d clock source as w ell as controlling the s tart function and monitoring the a /d converter end of convers ion status. t he acs 2 ~acs0 bi ts i n t he adcr0 re gister de fne t he adc i nput c hannel num ber. as t he device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs2~acs0 bits to determine which analog channel input pin is actually connected to the internal a/d converter. adcr0 register bit 7 6 5 4 3 2 1 0 ? a ? e start eocb adoff acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w por 0 1 1 0 0 0 bit 7 start : start the a/d conversion 010: start 01 : reset the a/d converter and set eocb to "1" this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module.
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 4~3 unimplemented, read as "0" bit 2~0 acs2~acs0 : select a/d channel 000: an0 001: an1 010: an2 011: an3 100: an4, it is connected to pin op1s0. 101: an5, it is connected to pin op1s1. 110: an6, it is connected to pin op1s2. 111: an7, it is connedted to op2o. adcr1 register bit 7 6 5 4 3 2 1 0 ? a ? e adck ? adck1 adck0 r/w r/w r/w r/w por 0 0 0 bit 7 ~3 unimplemented, read as "0" bit 2~0 adck2~adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. adcr2 register bit 7 6 5 4 3 2 1 0 ? a ? e vrps1 vrps0 vr ? s1 vr ? s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 vrps1, vrps0 : adc postive reference voltage selection 00: from a vdd 01: from advrh pin 1x: from bandgap bit 1~0 vrns1, vrns0 : adc negative reference voltage selection 00: from a vss 01: from advrl pin 1x: from daco pin
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the positive reference voltage supply to the a/d converter can be supplied from either the positive power sup ply p in, a vdd, o r f rom a n e xternal r eference sou rces su pplied o n p in advrh o r f rom bandgap output . the desired selection is made using the vprs[1:0] bit. the negative reference voltage supply to the a/d converter can be supplied from either the ground power supply pin, a v ss , or from an external reference sources supplied on pin advrl or from dac output . the desired selection is made using the vnrs[1:0] bit. t he advrh and advrl pins are pin-shared with other functions.
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs2~acs0 bits which are also contained in the adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure related i/o register. ? step 5 select p ositive a nd n egative r eference v oltage a t vr ps[1:0] a nd vr ns[1:0] b its f or adc reference voltage. ? step 6 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 7 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 8 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t ad where t ad is equal to the a/d clock period.
rev. 1.60 1 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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? ? ? ? - - ? ?? ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain s a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-s cale analog input value is equal to the v dd voltage, this gives a single bit analog input value of v dd divided by 4096. 1 lsb = v dd 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value v dd 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.
rev. 1.60 1?6 ?ove??e? ??? ?01? rev. 1.60 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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? ideal a/d transfer function a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a , 03h mov a dcr1, a ; select f sys /8 as a/d clock clr adoff mov a , 00h ; setup adcr0 register to confgure port as a/d inputs mov a dcr0, a ; and select an0 to be connected to the a/d converter : : start_conversion: clr s tart set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz e ocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp p olling_eoc ; continue polling mov a , adrl ; read low byte conversion result value mov a drl_buffer, a ; save result to user defned register mov a , adrh ; read high byte conversion result value mov a drh_buffer, a ; save result to user defned register : jmp s tart_conversion ; start next a/d conversion note: t o power off the adc, it is necessary to set adoff as "1".
rev. 1.60 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a , 03h mov a dcr1, a ; select f sys /8 as a/d clock clr adoff mov a , 00h ; setup adcr0 register to confgure port as a/d inputs mov a dcr0, a ; and select an0 to be connected to the a/d : : start_conversion: clr s tart set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_: mov ac c_stack, a ; save acc to user defned memory mov a , status mov s tatus_stack, a ; save status to user defned memory : : mov a , adrl ; read low byte conversion result value mov a drl_buffer, a ; save result to user defned register mov a , adrh ; read high byte conversion result value mov a drh_buffer, a ; save result to user defned register : : exit_isr: mov a , status_stack mov s tatus, a ; restore status from user defned memory mov a , acc_stack ; restore acc from user defned memory clr a df ; clear adc interrupt fag reti note: t o power off the adc, it is necessary to set adoff as "1".
rev. 1.60 1?8 ?ove??e? ??? ?01? rev. 1.60 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu audio dac the devices contain an internal 16-bit dac function which can be used for audio signal generation. audio output and volume control the voi ce da ta m ust be wri tten i nto re gister adal a nd adah. t he a udio out puts wi ll be wri tten into t he h igher n ibble o f adal a nd t he wh ole b yte o f adah. t here a re 8 sc ales o f v olume controllable level that are provided for the voltage type dac output. the programmer can change the volume by only writing the volume control data to the vol[2:0]. voice control bit the voice dac control bit adaen controls dac circuit enable/disable. if the dac circuit is not enabled, any adah/adal output is in valid. w riting a "1" to adaen bit is to enable dac circuit, and writing a "0" to adaen bit is to disable dac circuit. adac register bit 7 6 5 4 3 2 1 0 ? a ? e vol ? vol1 vol0 adae ? r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~5 vol2 ~ vol 0 : volume control bit 4~1 unimplemented, read as "0" bit 0 adaen : audio dac control 0: disabled 1: enabled when this bit is equal to "0", the audio dac enter power down mode. adal register bit 7 6 5 4 3 2 1 0 ? a ? e d3 d ? d1 d0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~ 4 d3~d0 : the bit[3:0] of data of audio dac bit 3~0 unimplemented, read as "0" adah register bit 7 6 5 4 3 2 1 0 ? a ? e d11 d10 d9 d8 d7 d6 d ? d ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d11~d4 : the bit[ 11 :4 ] of data of audio dac
rev. 1.60 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu digital to analog converter C dac this chip builds in 10-bit dac which provides 0 to 0.5 dacvref volt to the non-inverting input of op a, and is selected by dal and dah setting. it need a reference voltage which is decided by bgos[1:0]. dac register bit 7 6 5 4 3 2 1 0 ? a ? e dae ? r/w r/w por 0 bit 7 ~1 unimplemented, read as "0" bit 0 daen : 10-bit dac control 0: disabled 1: enabled dal register bit 7 6 5 4 3 2 1 0 ? a ? e d1 d0 r/w r/w r/w por 0 0 bit 7~ 6 d1, d0 : the b it[1:0] of data of 10-bit dac bit 5~0 unimplemented, read as "0" dah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 d7 d6 d ? d ? d3 d ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d9~d2 : the bit[ 9:2 ] of data of 10-bit dac
rev. 1.60 1?0 ?ove??e? ??? ?01? rev. 1.60 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu operational amplifer this c hip bui lds i n op a1 a nd op a2 for m easure a pplication. t he 10-bi t dac of fers a 0 t o 0.5 dac reference voltage to non-inverting input of op a1 and op a2. t he op a1 supports 3 dif ferent amplifcation by sw0~sw2 setting, and then outputs to channel 4~6 of adc. the op a2 is for temperature measure and external signal measure and outputs to channel 7 of adc. t he opa1 and opa2 are controlled by register opc1 and opc2 setting. the user can control switch 0~5 for vary application. please refer to register tsc for switch control. opc1 register bit 7 6 5 4 3 2 1 0 ? a ? e op1_aofm op1_ars op1e ? op1aof ? op1aof3 op1aof ? op1aof1 op1aof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 op1_aofm : input offset voltage cancellation mode and operational amplifer mode selection 0: operational amplifer mode 1: input offset voltage cancellation mode bit 6 op1_ars : operational amplifer input offset voltage cancellation reference selection bit 0: select op1n as the reference input 1: select op1p as the reference input when op1_aofm (s3c) = 0, s2c and s1c will be closed at the same time . when op1_aofm = 1, it will be set op1_ars to select op1p or op1n as a reference point . bit 5 op1en : operational amplifer 1 control 0: disabled 1: enabled bit 4~0 op1aof4 ~ op1aof 0 : operational amplifer input offset voltage cancellation control bits opc2 register bit 7 6 5 4 3 2 1 0 ? a ? e op ? _aofm op ? _ars op ? e ? op ? aof ? op ? aof3 op ? aof ? op ? aof1 op ? aof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 op2_aofm : input offset voltage cancellation mode and operational amplifer mode selection 0: operational amplifer mode 1: input offset voltage cancellation mode bit 6 op2_ars : operational amplifer input offset voltage cancellation reference selection bit 0: select op2n as the reference input 1: select op2p as the reference input when op2_aofm (s3c) = 0, s2c and s1c will be closed at the same time . when op2_aofm = 1, it will be set op2_ars to select op2p or op2n as a reference point . bit 5 op2en : operational amplifer 2 control 0: disabled 1: enabled bit 4~0 op2aof4 ~op2aof 0 : operational amplifer input offset voltage cancellation control bits
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bandgap the bandgap circuit is as followring figure, which consists of 8-bit dac, bandgap, op a and resis tors and provides accurate reference voltage to adc and dac, and output reference voltage is selected by bgos[1:0]. the 8-bit dac offer a more accurate reference voltage to other circuit. resisto?s mux ba?dgap 6.??k 11k 80k (if r-?r output i?pedance=?0k) dacvref 8-?its t?i? to 0.0??% t?i? to 3% 8-?it r-?r dac bgc register bit 7 6 5 4 3 2 1 0 ? a ? e bge ? bgos1 bgos0 r/w r/w r/w r/w por 0 0 0 bit 7 ~5 unimplemented, read as "0" bit 4 bgen : bandgap control 0: disable 1: enable when this bit is equal to 0, the bandgap enters power down mode. bit 3~2 unimplemented, read as "0" bit 1~0 bgos1, bgos0 : bandgap output selection. 0 x : 2.0v 10: a v dd 11: high impedance (foating) pvref register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~ 0 d7~d0 : 8-bit dac output for band gap fne turn
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu analog application circuit the analo g applic ation circuit is as followring fgure, which consists of 12-bit adc, bandgap, 10-bit dac, temperature sensor and operational amplifer for special function application. each function is described in the above section. when the analog application circuit is applied, please refer to this diagram. st?ip1 st?ip? 9'' advrl avss dacvref daco daco r1 r? r3 advrh r0 vg op1o op?o op?? op1? temp sensor an[3:0] op1s0 op1s1 op1s? 12-bit adc dac bandgap analog application diagram
rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu serial interface module C sim the devices conta in a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash memory , etc. the sim inte rface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control b its, n amed si m2~sim0, i n t he si mc0 r egister. t hese p ull-high r esistors o f t he si m p in- shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface this spi interface function which is contained within the serial interface module, should not be confused with the other independent spi function, known as spi1, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , but this device provided only one scs pin. if the mas ter needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared wi th n ormal i /o p ins a nd wi th t he i 2 c f unction p ins, t he spi i nterface m ust fr st b e e nabled b y selecting the sim enable confguration option and setting the correct bits in the simc0 and simc2 registers. after the spi confguration option has been confgured it can also be additionally disabled or enable d using the simen bit in the simc0 register . communication between devices connected to t he spi i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. spi master/slave connection
rev. 1.60 1?? ?ove??e? ??? ?01? rev. 1.60 1 ?? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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? ? ? ? ? spi block diagram the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several confguration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. another two spi confguration options determine if the csen and wcol bits are to be used. spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcke ? pckp1 pckp0 sime ? simcf simd d7 d6 d ? d ? d3 d ? d1 d0 simc ? d7 d6 ckpolb ckeg mls cse ? wcol trf spi registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register.
rev. 1.60 1 ? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? simd register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. ? simc0 register bit 7 6 5 4 3 2 1 0 ? a ? e sim ? sim1 sim0 pcke ? pckp1 pckp0 sime ? simcf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7 ~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to hi gh and shoul d therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states.
rev. 1.60 1?6 ?ove??e? ??? ?01? rev. 1.60 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 0 simcf: sim transfer incomplete fag for spi interface 0: no spi incomplete transfer occurs 1: spi incomplete transfer occurred the simcf bit is only used for the spi slave device to indicate whether the spi transfer is complete or not. when the spi transfer is in progress and the scs pin is set to 1, the spi transfer will be stopped and the simcf fag will be set to 1 by hareware. ? simc2 register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 ckpolb ckeg mls cse ? wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~6 d7, d6 : undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t det ermines the base condit ion of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inactive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable /disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol : spi w rite collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cle ared by the application program. note that using the wcol bit can be disabled or enabled via confguration option.
rev. 1.60 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 1?9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 0 trf: spi t ransmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set "1" automatically when an spi data transmission is complet ed, but must set to "0" by the applic ation program. it can be used to generate an interrupt. spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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rev. 1.60 1?8 ?ove??e? ??? ?01? rev. 1.60 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu

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rev. 1.60 160 ? ove ?? e ? ??? ? 01 ? rev. 1.60 161 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu i 2 c interface the i 2 c i nterface i s use d t o c ommunicate wi th e xternal pe ripheral de vices suc h a s se nsors e tc. originally de veloped by phi lips, i t i s a t wo l ine l ow spe ed se rial i nterface for sync hronous se rial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t h is de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a c onfguration op tion e xists t o a llow a c lock ot her t han t he syst em c lock t o dr ive t he i 2 c interface. another confguration option determines the debounce time of the i 2 c interface. this uses the internal clock to in ef fect add a debounce time to the external cloc k to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks.

rev. 1.60 160 ?ove??e? ??? ?01? rev. 1.60 161 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the micro controller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcke ? pckp1 pckp0 sime ? d0 simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d ? d ? d3 d ? d1 d0 simca iica6 iica ? iica ? iica3 iica ? iica1 iica0 d0 i 2 c registers list ? simc0 register bit 7 6 5 4 3 2 1 0 ? a ? e sim ? sim1 sim0 pcke ? pckp1 pckp0 sime ? d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7 ~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1~pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be
rev. 1.60 16 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 163 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bi t changes from low to hi gh and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 undefned bit, can be read or written by user software program. ? simc1 register bit 7 6 5 4 3 2 1 0 ? a ? e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. t his fag will be "1" when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receivera 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesti ng to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data.
rev. 1.60 16? ?ove??e? ??? ?01? rev. 1.60 163 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 1 iamwu : i 2 c address match w ake-up control 0: disable 1: enable this bit should be set to "1" to enable i 2 c address match wake up from sleep or idle mode. bit 0 rxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag ? simd register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown ? sima register bit 7 6 5 4 3 2 1 0 ? a ? e iica6 iica ? iica ? iica3 iica ? iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown bit 7 ~1 iica6 ~iica 0 : i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6 ~ bit 0. the si ma r egister i s a lso u sed b y t he spi i nterface b ut h as t he n ame si mc2. t he sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit, can be read or written by user software program. this bit can be read or written by user software program.

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rev. 1.60 16 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 16? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to "1" to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.

? ? ? ? ? ? - ?? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high.
rev. 1.60 16? ?ove??e? ??? ?01? rev. 1.60 16 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he haas bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then w rite data to the s imd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bi ts of da ta, t he re ceiver m ust t ransmit a n a cknowledge si gnal, l evel "0", be fore i t c an receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register . if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.60 166 ? ove ?? e ? ??? ? 01 ? rev. 1.60 167 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu
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- ? ? i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
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i 2 c bus isr flow chart
rev. 1.60 166 ?ove??e? ??? ?01? rev. 1.60 167 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu spi1 interface spi1 communication the spi1 interfac e is a full duplex synchronous serial data link. it is a four line interface with pin names sdi1, sdo1, sck1, scs1b0 and scs1b1. pins sdi1 and sdo1 are the serial data input and serial data output lines, sck1 is the serial clock line and scs1b0 and scs1b1 are the slave select line. as the spi1 interface pins are pin-shared with normal i/o pins, the spi1 interface must frst be enabled by selecting the spi1 enable confguration option and setting the correct bits in the spi1c0 and spi1c1 registe rs. after the spi1 confgurati on opt ion has been confgured it can al so be additionally disabled or enabled using the spi1en bit in the spi1c0 register . communication between devices connected to the spi1 interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. the scs1b0 a nd scs1b1 pi n a re c ontrolled by t he a pplication progra m, se t t he s1cse n bi t t o "1" to enable the scs1b0 and scs1b1 pin function and clear the s1csen bit to "0" to place the scs1b0 and scs1b1 pin into a foating state. sck 1 sdo 1 sdi 1 scs 1b0 scs 1b1 spi maste? spi slave spi slave sck sdi sdi scs sck sdi sdi scs spi1 master /slave bus connection the spi1 function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? sawcol and s1csen bit enabled or disable select the status of the spi1 interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as s1csen and spi1en.
rev. 1.60 168 ? ove ?? e ? ??? ? 01 ? rev. 1.60 169 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu spi1 registers there are three internal registers which control the overall operation of the spi 1 interface. these are the spi1 d data register and two registers spi1 c0 and spi1c1. register name bit 7 6 5 4 3 2 1 0 spi1c0 s1ms ? s1ms1 s1ms0 spicf spi1e ? s1cs spi1c1 s1ckpol s1ckeg s1mls s1cse ? s1wcol s1trf spi1d d7 d6 d ? d ? d3 d ? d1 d0 spi1 registers list ? spi1c0 register bit 7 6 5 4 3 2 1 0 ? a ? e s1ms ? s1ms1 s1ms0 spicf spi1e ? s1cs r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 bit 7 ~5 s1ms2~s1ms0 : master/slave clock select 000: spi1 master, f sys /4 001: spi1 master, f sys /16 010: spi1 master, f sys /64 011: spi1 master, f sub 100: spi1 master, tp0 ccrp match frequency/2 (pfd) 101: spi1 slave bit 4 unimplemented, read as 0 bit 3 spicf: spi1 interface transfer incomplete fag 0: no spi1 incomplete transfer occurs 1: spi1 incomplete transfer occurred the spicf bit is only used for the spi1 slave device to indicate whether the spi1 transfer is complete or not. when the spi1 transfer is in progress and the scs1b0 or scs1b1 pin is set to 1, the spi1 transfer will be stopped and the spicf fag will be set to 1 by hareware. bit 2 unimplemented, read as 0 bit 1 spi1en : spi1 enable or disable 0: disable 1: enable bit 0 s1cs : spi1 chip select pin 0: scs1b0 1: scs1b1
rev. 1.60 168 ?ove??e? ??? ?01? rev. 1.60 169 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? spi1c1 register bit 7 6 5 4 3 2 1 0 ? a ? e s1ckpol s1ckeg s1mls s1cse ? s1wcol s1trf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~6 unimplemented, read as "0" this bit can be read or written by user software program. bit 5 s1ckpol : determines the base condition of the clock line 0: sck 1 line will be high when the clock is inactive 1: sck 1 line will be low when the clock is inactive the s 1ckpol bit determines the bas e condition of the clock line, if the bit is high, then the sck1 line will be low when the clock is inactive. when the s1ckpol bit is low, then the sck1 line will be high when the clock is inactive. bit 4 s1ckeg : determines the spi1 sck1 active clock edge type s1ckpol = 0: 0: sck1 has high base level with data capture on sck1 rising edge 1: sck1 has high base level with data capture on sck1 falling edge s1ckpol = 1: 0: sck1 has low base level with data capture on sck1 falling edge 1: sck1 has low base level with data capture on sck1 rising edge the s1ckeg and s1ckpol bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. the s1ckpol bit determines the base condition of the clock line, if the bit is high, then the sck1 line will be low when the clock is inactive. when the s1ckpol bit is low , then the sc k1 l ine wi ll b e h igh wh en t he c lock i s i nactive. t he s1 ckeg b it d etermines active clock edge type which depends upon the condition of the s1ckpol bit . bit 3 s1mls : msb/lsb first bit 0: lsb shift frst 1: msb shift frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 s1csen : select signal enable/disable bit 0: scs1b0 and scs1b1 foating 1: enable the s1csen bit is used as an enable/disable for the scs1b0 and scs 1b1 pin. if this bit is low , then the s cs1b0 and s cs1b1 pin w ill be dis abled and placed into a foating condition . if the bit is high the scs1b0 and scs1b1 pin will be enabled and used as a select pin. note that using the s1csen bit can be disabled or enabled via confguration option. bit 1 s1wcol : w rite collision bit 0: collision free 1: collision detected the s1wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempte d to be written to the spi1d registe r during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the s1wcol bit can be disabled or enabled via confguration option. bit 0 s1trf : transmit/receive flag 0: not complete 1: t ransmission/reception complete the s1trf bit is the t ransmit/receive complete flag and is set "1" automatically when an spi1 data transmission is completed, but must set to zero by the application program. it can be used to generate an interrupt.
rev. 1.60 170 ? ove ?? e ? ??? ? 01 ? rev. 1.60 171 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? spi1d register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d ? d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 spi1 communication after t he spi1 i nterface i s e nabled by se tting t he spi1e n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the spi1d register , transmission/reception will begin simultaneously . when the data transfer i s c omplete, t he s 1 trf fa g wi ll b e se t a utomatically, b ut m ust b e c leared u sing t he a pplication program. in the slave mode, when the clock signal from the master has been received, any data in the spi1d register will be transmitted and any data on the sdi1 pin will be shifted into the spi1d register. the master should output a scs1bn signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs1bn signal depending upon the confgurations of the s1ckpol bit and s1ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the s1ckpol and s1ckeg bits. the spi1 will continue to function even in the idle mode. peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock . peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register . the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originat e from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/of f control, setting pcken bit to "1" enables the peripheral clock, and setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register . if the device enters the sleep mode , this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 ? a ? e sim ? sim1 sim0 pcke ? pckp1 pckp0 sime ? r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7 ~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e select ion and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device.
rev. 1.60 170 ?ove??e? ??? ?01? rev. 1.60 171 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1~pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bi t is the overall on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 and pintb pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd, sim, spi1 and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controll ed by a series of regi sters, locat ed in the special purpose dat a mem ory . the number of re gisters de pends upon t he de vice c hosen but fa ll i nto t hree c ategories. t he frst i s t he intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag.
rev. 1.60 17 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 173 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu function enable bit request flag notes glo ? al emi i ? tn pin i ? tne i ? tnf n=0 o ? 1 a/d conve ? te ? ade adf multi-function mfne mfnf n=0~3 ti ? e base tbne tbnf n=0 o ? 1 sim sime simf spi1 spi1e spi1f lvd lve lvf uart ure urf pi ? tb pin xpe xpf tm tnpe tnpf n=0~3 tnae tnaf n=0~3 tnbe tnbf n=1 interrupt register bit naming conventions interrupt register contents ? HT45F65 register name bit 7 6 5 4 3 2 1 0 i ? teg i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 i ? tc0 adf i ? t1f i ? t0f ade i ? t1e i ? t0e emi i ? tc1 mf ? f mf1f mf0f mf ? e mf1e mf0e i ? tc ? tb1f tb0f tb1e tb0e mfi0 t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe mfi1 urf spi1f lvf ure spi1e lve mfi ? t ? af t ? pf xpf simf t ? ae t ? pe xpe sime ? ht45f66/ht45f67 register name bit 7 6 5 4 3 2 1 0 i ? teg i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 i ? tc0 adf i ? t1f i ? t0f ade i ? t1e i ? t0e emi i ? tc1 mf3f mf ? f mf1f mf0f mf3e mf ? e mf1e mf0e i ? tc ? tb1f tb0f tb1e tb0e mfi0 t ? af t ? pf t0af t0pf t ? ae t ? pe t0ae t0pe mfi1 urf t1bf t1af t1pf ure t1be t1ae t1pe mfi ? t3af t3pf xpf simf t3ae t3pe xpe sime mfi3 spi1f lvf spi1e lve
rev. 1.60 17? ?ove??e? ??? ?01? rev. 1.60 173 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu integ register bit 7 6 5 4 3 2 1 0 ? a ? e i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~4 unimplemented, read as "0" bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int 0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 ? a ? e adf i ? t1f i ? t0f ade i ? t1e i ? t0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.60 17 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 17? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu intc1 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e mf ? f mf1f mf0f mf ? e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable intc1 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e mf3f mf ? f mf1f mf0f mf3e mf ? e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f: multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable
rev. 1.60 17? ?ove??e? ??? ?01? rev. 1.60 17 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu intc2 register bit 7 6 5 4 3 2 1 0 ? a ? e tb1f tb0f tb1e tb0e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 4 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 tb1e : time base 1 interrupt control 0: disable 1: enable bit 0 tb0e : time base 0 interrupt control 0: disable 1: enable mfi0 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 2 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: ena ble
rev. 1.60 176 ? ove ?? e ? ??? ? 01 ? rev. 1.60 177 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu mfi0 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e t ? af t ? pf t0af t0pf t ? ae t ? pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e uif spi1f lvf euti spi1e lve r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 uif : uart interrupt request fag 0: no request 1: interrupt request bit 6 u nimplemented, read as 0 bit 5 spi1f : spi1 interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 euti : uart interrupt control 0: disable 1: enable bit 2 unimplemented, read as 0 bit 1 spi1e : spi1 interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.60 176 ?ove??e? ??? ?01? rev. 1.60 177 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu mfi1 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e uif t1bf t1af t1pf euti t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 uif : u art interrupt request fag 0: no request 1: interrupt request bit 6 t1bf: tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 euti : uart interrupt control 0: disable 1: enable bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register (HT45F65) bit 7 6 5 4 3 2 1 0 ? a ? e t ? af t ? pf xpf simf t ? ae t ? pe xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf : sim interrupt request fag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable
rev. 1.60 178 ? ove ?? e ? ??? ? 01 ? rev. 1.60 179 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 0 sime : sim interrupt control 0: disable 1: enable mfi2 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e t3af t3pf xpf simf t3ae t3pe xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t3pf: tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf : sim interrupt request fag 0: no request 1: interrupt request bit 3 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 2 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable mfi3 register (ht45f66/ht45f67) bit 7 6 5 4 3 2 1 0 ? a ? e spi1f lvf spi1e lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 spi1f : spi1 interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 spi1e : spi1 interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.60 178 ?ove??e? ??? ?01? rev. 1.60 179 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p , comparator a or comparator b match or a/d conversion completion etc, the relevant interrupt request fag will be set. w hether t he r equest fa g a ctually g enerates a p rogram j ump t o t he r elevant i nterrupt v ector i s determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an act ual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.60 180 ? ove ?? e ? ??? ? 01 ? rev. 1.60 181 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu 0?h 08h 0ch 10h 1?h vector p? io ? ity high request flags ena ? le bits maste ? ena ? le request flags ena ? le bits emi auto disa ? led in isr inte ?? upt ? a? e inte ?? upt ? a? e emi emi emi emi emi t0af t0ae t0pf t0pe i ? t0f i ? t0 pin i ? t0e i ? t1f i ? t1 pin i ? t1e adf a/d ade mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e xxf legend request flag C no auto ? eset in isr xxf request flag C auto ? eset in isr xxe ena ? le bit t1af t1ae t1pf t1pe 18h 1ch ?0h low lvf lvd lve emi emi emi simf sime mf ?f m. funct. ? mf ?e tb0f ti ? e base 0 tb0e tb1f ti ? e base 1 tb1e spi1f spi1e t ? af tm ? a t ? ae t ? pf t ? pe xpf xpe spi1 pi ? tb pin tm ? p sim tm1 a tm1 p tm0 a tm0 p urf ure uart inte ?? upts contained within m ulti - function inte ?? upts 0?h 08h 0ch 10h 1?h vector p? io ? ity high request flags ena ? le bits maste ? ena ? le request flags ena ? le bits emi auto disa ? led in isr inte ?? upt ? a? e inte ?? upt ? a? e emi emi emi emi emi t0af t0ae t0pf t0pe i ? t0f i ? t0 pin i ? t0e i ? t1f i ? t1 pin i ? t1e adf a/d ade mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e xxf legend request flag C no auto ? eset in isr xxf request flag C auto ? eset in isr xxe ena ? le bit t1af t1ae t1pf t1pe 18h 1ch ?0h low lvf lvd lve emi emi emi simf sime mf ?f m. funct. ? mf ?e tb0f ti ? e base 0 tb0e tb1f ti ? e base 1 tb1e spi1f spi1e t ? af tm ? a t ? ae t ? pf t ? pe xpf xpe spi1 pi ? tb pin tm ? p sim tm1 a tm1 p tm0 a tm0 p urf ure uart inte ?? upts contained within m ulti - function inte ?? upts interrupt structure ? HT45F65
rev. 1.60 180 ?ove??e? ??? ?01? rev. 1.60 181 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu 04h 08h 0ch 10h 14h vector priority high request flags enable bits master enable request flags enable bits emi auto disabled in isr interrupt name interrupt name emi emi emi emi emi t1bf t1be t1af t1ae t1pf t1pe t0af t0ae t0pf t0pe int0f int0 pin int0e int1f int1 pin int1e adf a/d ade mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit t2af t2ae t2pf t2pe 18h 20h 24h low interrupts contained within multi - function interrupts mf3f m. funct. 3 mf3e emi 1ch lvf lvd lve emi emi emi simf sime mf2f m. funct. 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e spi1f spi1 e t3af tm3 a t3ae t3pf t3pe xpf xpe spi1 pintb pin tm3 p sim tm1 b tm1 a tm1 p tm2 a tm2 p tm0 a tm0 p urf ure uart interrupt structure ? ht45f66/ht45f67
rev. 1.60 18 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 183 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu external interrupt the external interrupts are controlled by signal transitions on the pins int0~int 1 . an external interrupt request will take place when the external interrupt request fags, int0f~int 1 f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int 1 e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int 1 f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi -function interrupt within the devices there are up to three or four multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources , namely the tm interrupts, ua rt interrupt, sim interrupt, spi1 interrupt, external peripheral interrupt and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, nam ely t he tm inte rrupts, uar t i nterrupt, sim inte rrupt, spi1 inte rrupt, ext ernal peripheral interrupt and l vd interru pt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.60 18? ?ove??e? ??? ?01? rev. 1.60 183 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.

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? ? time base interrupt tbc register bit 7 6 5 4 3 2 1 0 ? a ? e tbo ? tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0 : disable 1 : e nable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11 ~tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0 : disable (lxt quick start-up) 1 : e nable (lxt slow start-up) bit 2~0 tb02~tb00 : select t ime base 1 t ime-out period 0 00: 256/f tb 0 01: 512/f tb 0 10: 1024/f tb 0 11: 2048/f tb 1 00: 4096/f tb 1 01: 8192/f tb 1 10: 16384/f tb 1 11: 32768/f tb
rev. 1.60 18 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 18? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf , is set, which occurs when a byte of data has been received or transmitted by the sim interface. t o allow the program to branch to its res pective interrupt vector address , the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector , will take place. when the serial interface interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, howeve r only t he mul ti-function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the exte rnal peripheral interrupt operates in a similar way to the exter nal interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf , is set, which occurs when a negative edge transition appears on the pintb pin. t o allow the program to branch to its respective interrupt vector address, the global i nterrupt e nable bi t, e mi, e xternal pe ripheral i nterrupt e nable bi t, xpe , a nd a ssociated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full a nd a ne gative t ransition a ppears on t he e xternal peri pheral int errupt pi n, a subrout ine c all t o the re spective mu lti-function int errupt, wi ll t ake pl ace. w hen t he e xternal pe ripheral int errupt i s serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automa tically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with dif ferent functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin. serial peripheral interface interrupt the serial interface interrupt, also known as the spi1 interrupt, is contained within the multi- function interrupt. a sp i1 interrupt reques t w ill take place w hen the sp i1 interrupt reques t fag, spi1f, is set, which occurs when a byte of data has been received or transmitted by the spi1 interface. t o allow the program to branch to its res pective interrupt vector address , the global interrupt enable bit, emi, and the serial interface interrupt enable bit, spi1e, and multi-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of da ta ha s be en t ransmitted or re ceived by t he spi1 i nterface, a su broutine c all t o t he re spective multi-function interrupt vector , will take place. when the serial interface interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, howeve r only t he mul ti-function interrupt request fag will be also automatically cleared. as the spi1f fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.60 18? ?ove??e? ??? ?01? rev. 1.60 18 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard t ype tms have two interrupts each, while the enhanced t ype tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of t he com pact a nd st andard t ype t ms t here a re t wo i nterrupt re quest fa gs t npf a nd t naf a nd two enable bits tnpe and tnae. for the enhanced t ype tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. uart interrupt the uar t interrupt is contained within the multi-function interrupt. a uar t interrupt request will take plac e when the uar t interrupt request fag, urf , is set, which occurs when a byte of data has been received or transmitted by the sim interface or an error condition occurs. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the uart int errupt e nable bi t, ure , a nd mut i-function i nterrupt e nable bi ts, m ust frst be se t. w hen the interrupt is enabled, the stack is not full and a uar t interrupt condition occurs, a subroutine call t o t he re spective mul ti-function in terrupt ve ctor, wi ll t ake pl ace. w hen t he uar t in terrupt i s serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared . as the urf fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.60 186 ? ove ?? e ? ??? ? 01 ? rev. 1.60 187 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf3f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. t o return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.60 186 ?ove??e? ??? ?01? rev. 1.60 187 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu uart interface the devices conta in an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, asynchronous communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? separately enabled transmitter and receiver ? 2-byte deep fifo receive data buffer ? transmit and receive interrupts ? interrupts can be initialized by the following conditions: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect
uart data transfer scheme
rev. 1.60 188 ? ove ?? e ? ??? ? 01 ? rev. 1.60 189 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu uart external interface to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx . the tx pin is the u art trans mitter pin, w hich can be us ed as a general purpos e i/o or other pin-s hared functional pin if the pin is not configured as a u art trans mitter, w hich occurs when the txen bit in the ucr2 control register is equal to zero. similarly , the rx pin is the uart receiver pin, which can also be used as a general purpose i/o pin, if the pin is not confgured as a receiver , which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uarten bit, the txen and rxen bits, if set, will automatically setup these i/o pins or other pin- shared functional to their respective tx output and rx input conditio ns and disable any pull-high resistor option which may exist on the tx and rx pins. uart data transfer scheme the block diagram s hows the overall data trans fer s tructure arrangement for the u art interface. the a ctual da ta t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he application program. the data will then be transferred to the t ransmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator . only the txr register is mapped onto the mcu data memory , the transmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft re gister a t a ra te c ontrolled by t he ba ud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu dat a me mory, t he re ceiver shi ft re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr/rxr register is used for both data transmission and data reception. uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr/ rxr data registers. txr/rxr register the txr/rxr register is the data register which is used to store the data to be transmitted on the tx pin or being received from the rx pin. bit 7 6 5 4 3 2 1 0 ? a ? e txrx7 txrx6 txrx ? txrx ? txrx3 txrx ? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~0 txrx7~txrx0 : uart t ransmit/receive data bits
rev. 1.60 188 ?ove??e? ??? ?01? rev. 1.60 189 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu usr register the usr r egister i s t he st atus r egister f or t he uar t, wh ich c an b e r ead b y t he p rogram t o determine the present status of the uar t. all fags within the usr register are read only and further explanations are given below: bit 7 6 5 4 3 2 1 0 ? a ? e perr ? f ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fag is the noise fag. when this read only fag is 0, it indicates no noise condition. when the fag is 1, it indicates that the uart has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the nf fag can be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is 0, it indicates that there is no framing error. when the fag is 1, it indicates that a framing error has been detected for the current character. the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the receiver buffer has overfowed. when this read only fag is 0, it indicates that there is no overrun error. when the fag is 1, it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register. the fag is cleared by a software sequence, which is a read to the status register usr followed by an access to the rxr data register.
rev. 1.60 190 ? ove ?? e ? ??? ? 01 ? rev. 1.60 191 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the fag is 1, it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is 0, it indicates that the rxr read data register is empty. when the fag is 1, it indicates that the rxr read data register contains new data. when the contents of the shift register are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related fags nf, ferr, and/or perr are set within the same clock cycle. the rxif fag is cleared when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle fag is known as the transmission complete fag. when this read only fag is 0, it indicates that a transmission is in progress. this fag will be set to 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register. the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicates that the character is not transferred to the transmitter shift register. when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register. the txif fag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif fag bit will also be set since the transmit data register is not yet full.
rev. 1.60 190 ?ove??e? ??? ?01? rev. 1.60 191 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ucr1 register the ucr1 register together with the ucr2 register are the uar t control registers that are used to set the various options for the uar t function such as overall on/of f control, parity control, data transfer bit length, etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 ? a ? e uarte ? b ? o pre ? prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x: unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are i/o or other pin-shared functions 1: enable uart. tx and rx pins function as uart pins the uarten bit is the uart enable bit. when this bit is equal to 0, the uart will be disabled and the rx pin as well as the tx pin will be set as i/o or other pin- shared functions. when the bit is equal to 1, the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uart is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. in addition, the value of the baud rate counter will be reset. if the uart is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defned above. when the uart is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this bit is the parity function enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected.
rev. 1.60 19 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 193 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to 1, two stop bits format are used. if the bit is equal to 0, then only one stop bit format is used. bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is equal to 0, there are no break characters and the tx pin operats normally. when the bit is equal to 1, t here a re t ransmit b reak c haracters and t he t ransmitter wi ll se nd l ogic z eros. w hen this bit is equal to 1, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfes are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfes are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the uar t control registers and serves several purposes. one of its main functions is to control the basic enable/disable operation if the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 ? a ? e txe ? rxe ? brgh adde ? wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enable control 0: uart t ransmitter is disabled 1: uart t ransmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to 0, the transmitter will be disabled with any pending data transmissions being aborted. in addition the buffers will be reset. in this situation the tx pin will be used as an i/o or other pin-shared functional pin. if the txen bit is equal to 1 and the uarten bit is also equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. if this situation occurs, the tx pin will be used as an i/o or other pin-shared functional pin.
rev. 1.60 19? ?ove??e? ??? ?01? rev. 1.60 193 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to 0, the receiver will be disabled with any pending data receptions being aborted. in addition the receiver buffers will be reset. in this situation the rx pin will be used as an i/o or other pin-shared functional pin. if the rxen bit is equal to 1 and the uarten bit is also equal to 1, the receiver will be enabled and the rx pin will be controlled by the uart. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be used as an i/o or other pin-shared functional pin. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the baud rate register, brg, controls the baud rate of the uart. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detection function is disabled 1: address detection function is enabled the bit named adden is the address detection function enable control bit. when this bit is equal to 1, the address detection function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0, or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1, then the received word will be identifed as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the bno bit. if the address bit known as the 8th or 9th bit of the received word is 0 with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled the bit enables or disables the receiver wake-up function. if this bit is equal to 1 and the device is in idle or sleep mode, a falling edge on the rx pin will wake up the device. if this bit is equal to 0 and the device is in idle or sleep mode, any edge transitions on the rx pin will not wake up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled the bit enables or disables the receiver interrupt. if this bit is equal to 1 and when the receiver overrun fag oerr or received data available fag rxif is set, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the oerr or rxif fags.
rev. 1.60 19 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 19? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu bit 1 tiie : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled the bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when the transmitter idle fag tidle is set, due to a transmitter idle condition, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled the bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uart interrupt request fag will be set. if this bit is equal to 0, the uart interrupt request fag will not be infuenced by the condition of the txif fag. baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period o f wh ich i s d etermined b y t wo f actors. t he f irst o f t hese i s t he v alue p laced i n t he b rg register and the second is the value of the brgh bit within the ucr2 control register . the brgh bit decides, if the baud rate generat or is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register , n, which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) )] 1 ( 64 [ ? n f sys )] 1 ( 16 [ ? n f sys by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. brg register bit 7 6 5 4 3 2 1 0 ? a ? e brg7 brg6 brg ? brg ? brg3 brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~0 brg7 ~brg0: baud rate values by programming the brgh bit in the ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup.
rev. 1.60 19? ?ove??e? ??? ?01? rev. 1.60 19 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = )] 1 ( 64 [ ? n f sys n 1 ) 64 ( ? ? br f sys f 0208 . 12 1 ) 64 4800 ( 4000000 ? ? ? ? 4808 )] 1 12 ( 64 [ 4000000 ? ? 4800 4800 4808 ? baud rate k/bps baud rates for brgh=0 f sys =4mhz f sys =3.579545mhz f sys =7.159mhz brg kbaud error(%) brg kbaud error(%) brg kbaud error(%) 0.3 ? 07 0.300 0.16 18 ? 0.300 0.00 1. ? ? 1 1. ? 0 ? 0.16 ? 6 1.190 -0.83 9 ? 1. ? 03 0. ? 3 ? . ? ?? ? . ? 0 ? 0.16 ?? ? . ? 3 ? 1.3 ? ? 6 ? .380 -0.83 ? .8 1 ? ? .808 0.16 11 ? .661 - ? .90 ?? ? .863 1.3 ? 9.6 6 8.9 ? 9 -6.99 ? 9.3 ? 1 - ? .90 11 9.3 ?? - ? .90 19. ? ? ? 0.833 8. ? 1 ? 18.6 ? 3 - ? .90 ? 18.6 ? 3 - ? .90 38. ? ? 3 ? . ? 86 - ? .90 ? 7.6 0 6 ? . ? 00 8. ? 1 0 ?? .930 - ? .90 1 ?? .930 - ? .90 11 ? . ? 0 111.8 ? 9 - ? .90 baud rates and error values for brgh=0 baud rate k/bps baud rates for brgh=1 f sys =4mhz f sys =3.579545mhz f sys =7.159mhz brg kbaud error(%) brg kbaud error(%) brg kbaud error(%) 0.3 1. ? ? 07 1. ? 0 ? 0.16 18 ? 1. ? 03 0. ? 3 ? . ? 103 ? . ? 0 ? 0.16 9 ? ? . ? 06 0. ? 3 18 ? ? . ? 06 0. ? 3 ? .8 ? 1 ? .808 0.16 ? 6 ? .76 -0.83 9 ? ? .811 0. ? 3 9.6 ?? 9.61 ? 0.16 ?? 9.7 ? 7 1.3 ? ? 6 9. ?? 0 -0.83 19. ? 1 ? 19. ? 31 0.16 11 18.6 ? 3 - ? .90 ?? 19. ??? 1.3 ? 38. ? 6 3 ? .71 ? -6.99 ? 37. ? 86 - ? .90 11 37. ? 86 - ? .90 ? 7.6 3 6 ? . ? 8. ? 1 3 ?? .930 - ? .90 7 ?? .930 - ? .90 11 ? . ? 1 1 ?? 8. ? 1 1 111.86 - ? .90 3 111.86 - ? .90 ?? 0 0 ?? 0 0 baud rates and error values for brgh=1
rev. 1.60 196 ? ove ?? e ? ??? ? 01 ? rev. 1.60 197 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is compos ed of one s tart bit, eight or nine data bits and one or tw o s top bits . p arity is supporte d by t he uar t hardwa re and ca n be se tup t o be eve n, odd or no pari ty. for the m ost common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with the parity , are setup by programming the corresponding bno, pr t, pren and st ops bits in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the transmitter and receiver of the uart are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart interface the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing t he uar ten b it wi ll d isable t he t x a nd r x p ins a nd t hese t wo p ins wi ll b e u sed a s a n i/o or other pin-shared functional pin. when the uar t function is disabled, the buf fer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the enable control, the error and status fags with bits txen, rxen, txbrk, rxif, oe rr, fe rr, pe rr and nf bei ng cl eared whi le bi ts t idle, t xif and ridle wi ll be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 regi ster is cle ared while the uar t is act ive, then al l pendi ng transmissions and receptions will be immediately suspended and the uar t will be reset to a condition as defned above. if the uar t is then subsequently re-enabled, it will restart again in the same confguration. data, parity and stop bit selection the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9. the pr t bit controls the choice if odd or even parity . the pren bit controls the parity on/of f function. the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address detect mode control bit identif es the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 1 1 example of 8-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 trams,otter receiver data format
rev. 1.60 196 ?ove??e? ??? ?01? rev. 1.60 197 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.

uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s de fned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. the tx output pin will then return to the i/ o or other pin-shared function. transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the least signifcant bit lsb frst. in the transmit mode, the txr register forms a buf fer between the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the uart transmitter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution
rev. 1.60 198 ? ove ?? e ? ??? ? 01 ? rev. 1.60 199 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set, then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register , which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmitting break if the txbrk bit is set, then the break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13xn 0 bits, where n=1, 2, etc. if a break character is to be transmitted, then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept a t a l ogic hi gh l evel, t hen t he t ransmitter c ircuitry wi ll t ransmit c ontinuous bre ak c haracters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver the uart is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register . when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, will be stored in the rx8 bit in the ucr1 register . at the receiver core lies the receiver shift register more commonly known as the rsr. the data which is receive d on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin to the shift register , with the lea st signifcant bit lsb frst. the rxr register is a four byte deep fifo da ta buf fer, whe re four byt es c an be he ld i n t he fifo whi le t he 5t h byt e c an c ontinue t o be received. note that the application program must ensure that the data is read from rxr before the 5th b yte h as b een c ompletely sh ifted i n, o therwise t he 5 th b yte wi ll b e d iscarded a nd a n o verrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits.
rev. 1.60 198 ?ove??e? ??? ?01? rev. 1.60 199 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received, the following sequence of events will occur: ? the rxif bit in the usr register will be set then rxr register has data available, at least three more character can be read. ? when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. a rxr register read execution receiving break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and st ops bits. if the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cifed by bno a nd st ops. t he rxif bi t i s se t, fe rr is set, zeros are loaded into the rece ive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the ass umption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uar t registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an i nterrupt i s ge nerated i f rie =1, whe n a word i s t ransferred from t he re ceive shi ft register, rsr, to the receive data register , rxr. an overrun error can also generate an interrupt if rie=1.
rev. 1.60 ? 00 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?01 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr the rxr register is composed of a four byte deep fifo data buf fer, where four bytes can be held in the fifo register , while a 5th byte can continue to be received. before the 5th byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register. noise error C nf over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame, the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are selecte d, both stop bits must be high. otherwise the ferr fag will be set. the ferr fag is buffered along with the received data and is cleared in any reset. parity error C perr the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity function is enabled, pren=1, and if the parity type, odd or even, is s elected. the read only p err f ag is buf fered along w ith the received data bytes. it is cleared on any reset, it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word.
rev. 1.60 ?00 ?ove??e? ??? ?01? rev. 1.60 ? 01 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu uart interrupt structure several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt cont rol is enabled and the stac k is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be serviced before returning to the main program. four of thes e conditions h ave t he c orresponding usr r egister fa gs wh ich wi ll g enerate a uar t i nterrupt i f i ts associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whi ch i s al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is e nabled by se tting t he adde n bi t i n t he ucr2 re gister. an rx pi n wa ke-up, whi ch i s a lso a uart interrupt source, does not have an associated flag, but will generate a uar t interrupt if the microcontroller is woken up by a falling edge on the rx pin, if the w ake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interr upt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed.
? ? ?? ? ? ? ?? ? ? ? ? ? - ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uart interrupt scheme
rev. 1.60 ? 0 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?03 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu address detect mode setting the address detect function enable control bit, adden, in the ucr2 register , enables this special function. if this bit is set to 1, then an additional qualifer will be placed on the generation of a re ceiver da ta a vailable i nterrupt, whi ch i s re quested by t he rxif fl ag. if t he adde n bi t is equal to 1, then w hen the data is available, an interrupt w ill only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit of the microcontroller must also be enabled for correct interrupt generation. the highest address bit is the 9th bit if the bit bno=1 or the 8th bit if the bit bno=0. if the highest bit is high, then the received word wi ll be de fned a s a n a ddress ra ther t han da ta. a da ta a vailable i nterrupt wi ll be ge nerated every tim e the last bit of the receiv ed word is set. if the adden bit is equal to 0, then a receive data a vailable interrupt will be generated each time the rxif fag is set, irrespective of the data last but status. the address detection and parity functions are mutually exclusive functions. therefore, if the address detect function is enable d, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit pren to zero. adden bit 9 if bno=1 bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 x 1 adden bit function uart power down mode and wake-up when the mcu is in the power down mode, the uar t will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be paused until the uar t clock source derived from the microcontroller is activated. in a similar way , if the mcu enters the power down mode while receiving data, then the reception of data will likewise be paused. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be af fected. it is recommended to make sure frst that the uar t data transmission or reception has been fnished before the microcontroller enters the power down mode. the ua rt function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falli ng edge on the rx pin will wake up the mcu from the power down mode . note that as it t akes certa in system cl ock cycl es after a wake-up, before norma l microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, the multi-function interrupt enable bit, mf1e, and the uar t interrupt enable bit, ure, must also be set. if the emi and mf1e bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wa ke-up b efore n ormal m icrocontroller r esumes, t he uar t i nterrupt wi ll n ot b e g enerated until after this time has elapsed.
rev. 1.60 ?0? ?ove??e? ??? ?01? rev. 1.60 ? 03 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low volta ge conditionwill be determ ined. a low voltage condition is indicatedwhen the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 ? a ? e lvdo lvde ? vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2 ~ vlvd0 : select lvd v oltage 000 : 2.0v 00 1: 2.2v 010 : 2.4v 011 : 2.7v 100 : 3.0v 101 : 3.3v 110 : 3.6v 111 : 4.0v
rev. 1.60 ? 0 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?0? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltagewhich will be automatically enabled.when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when l vd functi on is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.60 ?0? ?ove??e? ??? ?01? rev. 1.60 ? 0 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lcd driver for lar ge volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs signifcantly . however , the corresponding com and seg signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur . the device contain s an lcd driver function, which with their internal lcd signal generating circuitry and various options, will automatically generate these time and amplitu de varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. this device includ e s a wide range of options to enable lcd displays of various types to be driven. the table shows the range of options available across the device range. part no. duty bias b ias type w ave type ht ?? f6 ? 1/ ? 1/3 c a o ? b ht ?? f66 ht ?? f67 1/ ? 1/3 c a o ? b 1/6 c type and 1/3 bias, v as = ?1 v ab = 3/2 xv lcd = v a v b = v lcd v c = 1/2 x v lcd charge pump v max v lcd v a v b v c 0.1f 0.1f 0.1f c1 c2 v ab v c c type and 1/3 bias, v as = ? 0 v a = v lcd v ab = 2/3 x v lcd = v b v c = 1/3 x v lcd charge pump 0.1f 0.1f 0.1f v max v lcd v a v b v c c1 c2 v ab v c c type bias voltage levels note: f v as = "1", v lcd = v and v max = v ab if v as = "0", v lcd = v max = v
rev. 1.60 ? 06 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?07 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lcd memory an area of data memory is especia lly reserved for use for the lcd display data. this data area is known as the lcd memory . any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary lcd driving signals. there - fore a ny da ta wri tten i nto t his me mory wi ll be i mmediately re fected i nto t he a ctual di splay c on - nected to the microcontroller. as the lcd memory addresses overlap those of the general purpose data memory , it s stored in its own independent bank 1 area. the data memory bank to be used is chosen by using the bank pointer, which i s a sp ecial f unction r egister i n t he da ta me mory, wi th t he n ame, b p. t o a ccess t he l cd memory therefore requires frst that bank 1 is selected by writing a value of 01h to the bp register . after this, the memory can then be accessed by using indirect addressing through the use of memory pointer mp1. w ith bank 1 selected, then using mp1 to read or write to the memory area, starting with address 80h, will result in operations to the lcd memory . directly addressing the display memory is not applicable and will result in a data access to the bank 0 general purpose data memory. the accompanying lcd memory map diagrams shows how the internal lcd memory is mapped to t he se gments a nd commons of the d isplay fo r t he d evice. l cd me mory maps for t he d evice wi th smaller memory capacities can be extrapolated from these diagrams. com0 com3 com? com1 . . seg 0 80 h . . seg ?3 97h lcd ram ( 24 seg x 4 com ) b0 b1 b7 b6 b? b? b3 b? . . . . . . . . . . . . . . lcd memory map ? HT45F65 com0 com? com? com3 com? com1 . . seg0 seg?9 seg?8 seg1 80h 9dh 9ch 81h . . . . seg31 seg30 9fh 9eh com0 com3 com? com1 . . seg0 seg?9 seg?8 seg1 80h 9dh 9ch 81h . . . . seg31 seg30 9fh 9eh b0 b1 b7 b6 b? b? b3 b? lcd ram (30 seg x 6 com) lcd ram (32 seg x 4 com) b0 b1 b7 b6 b? b? b3 b? lcd me?o?y map ? ht45f66/ht45f67
rev. 1.60 ?06 ?ove??e? ??? ?01? rev. 1.60 ? 07 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu lcd registers control regis ters in the d ata m emory, are us ed to control the various s etup features of the lcd driver. there is one control register for the lcd function, lcdc. various bits in this registers control functions such as duty type, overall lcd enable and disable. the lcden bit in the lcdc register , which provides the overall lcd enable/disable function, will only be ef fective when the device is in the normal, slow or idle mode. if the device is in the sleep mode then the display will always be disabled. the type bit in the same register is used to select whether t ype a or t ype b lcd control signals are used. lcdc register ? HT45F65 bit 7 6 5 4 3 2 1 0 ? a ? e type vas lcde ? r/w r/w r/w r/w por 0 0 0 bit 7 type : lcd t ype control 0: t ype a 1: t ype b bit 6 va s : v a voltage selection for c type lcd 0: v a equals v dd 1: v a equals 1.5 v dd bit 5~1 unimplemented, read as 0 bit 0 lcden : lcd enable control 0: disable 1: enable in the normal, slow or idle mode, the lcd on/of f function can be controlled by this bit. in the sleep mode, the lcd is always off. lcdc register ? ht45f66/ ht45f67 bit 7 6 5 4 3 2 1 0 ? a ? e type vas dyt lcde ? r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 type : lcd t ype control 0: t ype a 1: t ype b bit 6 va s : v a voltage selection for c type lcd 0: v a equals v dd 1: v a equals 1.5 v dd bit 5 dyt : lcd duty control 0: 1/4 duty, 32seg 4com 1: 1/6 duty, 30seg 6com bit 4~1 unimplemented, read as "0" bit 0 lcden : lcd enable control 0: disable 1: enable in the normal, slow or idle mode, the lcd on/of f function can be controlled by this bit. in the sleep mode, the lcd is always off.
rev. 1.60 ? 08 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?09 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu clock source the lcd clock source is the internal clock signal, f sub , divided by 8, using an internal divider circuit. the f sub internal clock is supplied by either the lirc or lxt oscillator , the choice of which is determined by a confguration option. for proper lcd operation, this arrangement is provided to generate an ideal lcd clock source frequency of 4khz. f sub clock source lcd clock frequency lirc ? khz lxt ? khz lcd clock source lcd driver output the number of com and seg outputs supplied by the lcd driver , as well as its duty selections, is dependent upon how the lcd control bits are programmed. the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this dif ferential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and a pplied t o t he a pplication l cd. t hese t ime a nd a mplitude va rying si gnals a re a utomatically generated by the lcd driver circui ts in the microcontroller . what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty , which is chosen by a control bit to have a value of 1/3 and which equates to a com number of 3, therefore defnes the number of time divisions within each lcd signal frame. t wo types of signal generation are also provided, known as t ype a and t ype b, the required type is selected via the type bit in the lcdc register . t ype b of fers lower frequency signals, however lower frequencies may introduce fickering and infuence display clarity. lcd waveform timing diagrams the a ccompanying t iming di agrams de pict t he di splay dri ver si gnals ge nerated by t he microcontroller for various values of duty . the huge range of various permutations only permits a few types to be displayed here.
rev. 1.60 ?08 ?ove??e? ??? ?01? rev. 1.60 ? 09 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu v a v b v c v ss 1 frame v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss com0 com1 com2 all segments off com0 segments on com3 com1 segments on com2 segments on (other combinations are omitted) com0, 1 segments on com3 segments on normal operation mode during reset or lcd off com0, com1, com2, com3 all segment outputs v a v b v c v ss v a v b v c v ss v a v b v c v ss com0, 2 segments on v a v b v c v ss com0, 3 segments on v a v b v c v ss all segments on lcd off lcd driver output (1/4 duty, 1/3 bias, a-type waveform) note: 1. for 1/3 c type bias, v a =v lcd 1.5, v =v lcd and v c =v lcd 1/2. 2. the lcd function can be as on or off by software control.
rev. 1.60 ? 10 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ? 11 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu v a v b v c v ss 1 frame v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss v a v b v c v ss com0 com1 com2 all segments are off com0 side segments are on com3 com1 side segments are on com2 side segments are on (other combinations are omitted) com0, 1 side segments are on com3 side segments are on normal operation mode during reset or lcd off com0, com1, com2, com3 all segment outputs v a v b v c v ss v a v b v c v ss v a v b v c v ss com0, 2 side segments are on v a v b v c v ss com0, 3 side segments are on v a v b v c v ss all segments are on lcd off lcd driver output (1/4 duty, 1/3 bias, b-type waveform) note: 1. for 1/3 c type bias, v a =v lcd 1.5, v =v lcd and v c =v lcd 1/2. 2. the lcd function can be as on or off by software control.
rev. 1.60 ?10 ?ove??e? ??? ?01? rev. 1.60 ? 11 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialised after the microcontroller is powered on. like the general purpose data memory , the contents of the lcd memory are in an unknown condition after power - on. as t he c ontents of t he l cd me mory wi ll be m apped i nto t he a ctual di splay, i t i s i mportant t o initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as t he l oad pre sented t o t he m icrocontroller by l cd pi xels c an be ge nerally m odeled a s m ainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. one additional consideration that must be taken into account is what happens when the microcontroller enters the idle or slow mode. the lcden control bit in the lcdc register permits the di splay t o be powe red of f t o re duce powe r c onsumption. if t his bi t i s z ero, t he dri ving si gnals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the lcd. after power -on, note that as the lcden bit will be cleared to zero, the display function will be disabled. lcd panel equivalent circuit
rev. 1.60 ? 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?13 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu temperature sensor this chip builds in temperature sensor and switchs for temperature measure application. when switch 5 is close and switch 4 is open, the output signal of temperature sensor will output to channel 7 of adc via opa2. all switchs is controlled in tsc register. tsc register bit 7 6 5 4 3 2 1 0 ? a ? e tse ? sw ? sw ? sw3 sw ? sw1 sw0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tsen : temperature sensor control 0: disabled 1: enabled bit 6 unimplemented, read as "0" bit 5 sw5 : switch 5 control 0: open 1: close this bit is for strip2 measure. bit 4 sw4 : switch 4 control 0: open 1: close this bit is for temperature sensor. bit 3 sw3 : switch 3 control 0: open 1: close when this bit is close, the vg pin connects to ground. bit 2 sw2 : switch 2 control 0: open 1: close when this bit is close, the op1s2 pin connects to op1o pin bit 1 sw1 : switch 1 control 0: open 1: close when this bit is close, the op1s1 pin connects to op1o pin bit 0 sw0 : switch 0 control 0: open 1: close when this bit is close, the op1s0 pin connects to op1o pin
rev. 1.60 ?1? ?ove??e? ??? ?01? rev. 1.60 ? 13 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu application circuit application block diagram seg [ 31 :0] com [3:0] vab vc c1 c? voice rom sdo 1 sdi 1 sck 1 scs 0 aud sdi / sda sdo sck / scl scs pck / tx pi?tb / rx glucose ? u?ic acid ? choleste?ol test st?ips pb 3/ a? 1 pb ?/ a? 0 dacvref daco op 1o op 1s0 op 1s1 op 1s? pb 1/ op 1? pb 0/ op ?o pb ?/ a? ? pb ?/ a? 3 xt ? xt 1 ocdsck / res vdd vss avdd avss pa 3 pa ? pa ? pa 6 pb 1 key usb b?idge a?plifie? rs ?3? t?ansceive? lcd panel glucose measu?e ci?cuit strip1 strip2 avdd advrl avss dacvref daco daco r1 r2 r3 advrh r0 vg op1o op2o op2n op1n temp sensor an[3:0] op1s0 op1s1 op1s2 12-bit adc dac bandgap note: for higher precision application requirements, it is recommended to use an external voltage reference source (connected to dac vref pin).
rev. 1.60 ? 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?1? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.60 ?1? ?ove??e? ??? ?01? rev. 1.60 ? 1 ? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.60 ? 16 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?17 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov addm a ? [ ? ] add acc to data me ? o ? y 1 ? ote z ? c ? ac ? ov add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 ? ote z ? c ? ac ? ov sub a ? x su ? t ? act i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov sub a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov subm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov sbc a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov sbcm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov daa [ ? ] deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 ? ote c logic operation a ? d a ? [ ? ] logical a ? d data me ? o ? y to acc 1 z or a ? [ ? ] logical or data me ? o ? y to acc 1 z xor a ? [ ? ] logical xor data me ? o ? y to acc 1 z a ? dm a ? [ ? ] logical a ? d acc to data me ? o ? y 1 ? ote z orm a ? [ ? ] logical or acc to data me ? o ? y 1 ? ote z xorm a ? [ ? ] logical xor acc to data me ? o ? y 1 ? ote z a ? d a ? x logical a ? d i ?? ediate data to acc 1 z or a ? x logical or i ?? ediate data to acc 1 z xor a ? x logical xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 ? ote z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement i ? ca [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc 1 z i ? c [ ? ] inc ? e ? ent data me ? o ? y 1 ? ote z deca [ ? ] dec ? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] dec ? e ? ent data me ? o ? y 1 ? ote z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 ? one rr [ ? ] rotate data me ? o ? y ? ight 1 ? ote ? one rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 ? ote c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 ? one rl [ ? ] rotate data me ? o ? y left 1 ? ote ? one rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 ? ote c
rev. 1.60 ?16 ?ove??e? ??? ?01? rev. 1.60 ? 17 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 ? one mov [ ? ] ? a move acc to data me ? o ? y 1 ? ote ? one mov a ? x move i ?? ediate data to acc 1 ? one bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 ? ote ? one set [ ? ].i set ? it of data me ? o ? y 1 ? ote ? one branch jmp add ? ju ? p unconditionally ? ? one sz [ ? ] skip if data me ? o ? y is ze ? o 1 ? ote ? one sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 ? ote ? one sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 ? ote ? one s ? z [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 ? ote ? one siz [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one sdz [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one siza [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one sdza [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one call add ? su ?? outine call ? ? one ret retu ? n f ? o ? su ?? outine ? ? one ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? ? one reti retu ? n f ? o ? inte ?? upt ? ? one table read tabrd [ ? ] read table (specifc page) to tblh and data memory ? ? ote ? one tabrdc [ ? ] read ta ? le (cu ?? ent page) to tblh and data me ? o ? y ? ? ote ? one tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? ? ote ? one miscellaneous ? op ? o ope ? ation 1 ? one clr [ ? ] clea ? data me ? o ? y 1 ? ote ? one set [ ? ] set data me ? o ? y 1 ? ote ? one clr wdt clea ? watchdog ti ? e ? 1 to ? pdf clr wdt1 p ? e-clea ? watchdog ti ? e ? 1 to ? pdf clr wdt ? p ? e-clea ? watchdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 ? ote ? one swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 ? one halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for t he clr w dt1 a nd clr w dt2 i nstructions t he t o a nd pdf fa gs m ay be a ffected by t he execution status. the t o and pdf fags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.60 ? 18 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?19 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.60 ?18 ?ove??e? ??? ?01? rev. 1.60 ? 19 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.60 ?? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ??1 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.60 ??0 ?ove??e? ??? ?01? rev. 1.60 ?? 1 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.60 ??? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ??3 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.60 ??? ?ove??e? ??? ?01? rev. 1.60 ?? 3 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.60 ??? ? ove ?? e ? ??? ? 01 ? rev. 1.60 ??? ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.60 ??? ?ove??e? ??? ?01? rev. 1.60 ??? ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.60 ?? 6 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ??7 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.60 ??6 ?ove??e? ??? ?01? rev. 1.60 ?? 7 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.60 ?? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ??9 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.3 ?? bsc b 0. ? 76 bsc c 0.3 ?? bsc d 0. ? 76 bsc e 0.0 ? 0 bsc f 0.007 0.009 0.011 g 0.0 ? 3 0.0 ?? 0.0 ? 7 h 0.063 i 0.00 ? 0.006 j 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0. ? 0 bsc f 0.17 0. ?? 0. ? 7 g 1.3 ? 1. ? 0 1. ?? h 1.60 i 0.0 ? 0.1 ? j 0. ?? 0.60 0.7 ? k 0.09 0. ? 0 0 D 7
rev. 1.60 ??8 ?ove??e? ??? ?01? rev. 1.60 ?? 9 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.3 ?? bsc b 0. ? 76 bsc c 0.3 ?? bsc d 0. ? 76 bsc e 0.016 bsc f 0.00 ? 0.007 0.009 g 0.0 ? 3 0.0 ?? 0.0 ? 7 h 0.063 i 0.00 ? 0.006 j 0.018 0.0 ?? 0.030 k 0.00 ? 0.008 0 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0. ? 0 bsc f 0.13 0.18 0. ? 3 g 1.3 ? 1. ? 0 1. ?? h 1.60 i 0.0 ? 0.1 ? j 0. ?? 0.60 0.7 ? k 0.09 0. ? 0 0 7
rev. 1.60 ? 30 ? ove ?? e ? ??? ? 01 ? rev. 1.60 ?31 ?ove??e? ??? ?01? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a D 0. ? 7 ? bsc D b D 0.39 ? bsc D c D 0. ? 7 ? bsc D d D 0.39 ? bsc D e D 0.016 bsc D f 0.007 0.009 0.011 g 0.0 ? 3 0.0 ?? 0.0 ? 7 h D D 0.063 i 0.00 ? D 0.006 j 0.018 0.0 ?? 0.030 k 0.00 ? D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 1 ? .00 bsc b 10.00 bsc c 1 ? .00 bsc d 10.00 bsc e D 0. ? 0 bsc D f 0.13 0.18 0. ? 3 g 1.3 ? 1. ? 1. ?? h D D 1.60 i 0.0 ? 0.1 ? j 0. ?? 0.60 0.7 ? k 0.09 D 0. ? 0 0 D 7
rev. 1.60 ?30 ?ove??e? ??? ?01? rev. 1.60 ? 31 ? ove ?? e ? ??? ? 01 ? HT45F65/ht45f66/ht45f67 glucose meter 8-bit flash mcu copy ? ight ? ? 01 ? ? y holtek semico ? ductor i ? c. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e accu ? ate at the ti ? e of pu ? lication. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that such applications will ? e suita ? le without fu ? the ? ? odification ? no ? ? eco ?? ends the use of its p ? oducts fo ? application that ? ay p ? esent a ? isk to hu ? an life due to ? alf unction o ? ot he ? wis e. holtek's p ? oduc ts a ? e not autho ? iz ed fo ? use as c ? it ical co ? ponents in life suppo ? t devices o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek.co ? .

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